Bi-directional State Machine Buffers With Data Manipulation Mechanisms
Publication Date: 2016-Apr-21
The IP.com Prior Art Database
Disclosed is a bi-directional state machine buffer mechanism to process transactions in memory or I/O subsystem hardware in a computer system. Using this mechanism, a single hardware state machine can easily coordinate transactions in different directions and support more complex operations such as byte masked write, loop back, and arithmetic operations.
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--directional State Machine Buffers With Data Manipulation Mechanisms
directional State Machine Buffers With Data Manipulation Mechanisms
In a computer system, often memory or I/O subsystem hardware has an array of state machines (SMs) to keep track of ongoing transactions. For example, when a hardware unit reads multiple memory blocks, the unit assigns an SM for each of these outstanding read requests. Each SM keeps track of the assigned read request and takes necessary actions as needed, until the read data comes back and request completes. Also, often such a hardware unit has buffers (e.g., using on-chip SRAM arrays) to store data temporarily. For example, when a unit issues a memory read, a buffer entry will be used for storing the read data from the memory. Each SM owns a certain entry in the buffer and uses the entry for processing transactions. Each SM, and hence the corresponding buffer entry, operates independently with each other to process multiple outstanding requests in parallel.
In existing systems [1, 2], simply one SM is associated with one buffer entry. Typically buffers and SMs on different directions (e.g., read and write) were separated and operated independently. This hardware structure was enough to support simple transactions such as plain reads and writes. However, recent computer systems are required to support more complex functions. As a result, sometimes hardware has to manage and coordinate transactions in different directions in a centralized manner, rather than handling them independently. The traditional simple SM and buffer structures no longer work properly in such situations. In addition, sometimes hardware needs to manipulate data across different directions. For example, to perform an in-memory atomic operation, an SM buffers both memory read data and the arithmetic operand at the same time. Subsequently, arithmetic logic unit (ALU) performs operation using the buffered data.
Bi-directional buffers managed by a single state machine:
Proposed is a mechanism in which each SM owns multiple buffer entries on different directions of data flow, and manipulates data across these buffer entries. The figure below shows an embodiment of the proposed buffer mechanism in an example use case of memory system proxy interface. This proxy hardware bridges across multiple memory systems. One side can access the memory on the other side via the bridge. An example use case would be to connect accelerator hardware to the main processor's memory system.