Browse Prior Art Database

Array Architecture to Mitigate Solder Reflow data loss in MRAM

IP.com Disclosure Number: IPCOM000246044D
Publication Date: 2016-Apr-28
Document File: 6 page(s) / 549K

Publishing Venue

The IP.com Prior Art Database

Abstract

A new array architecture is described to mitigate the tough requirement to ensure data integrity after a solder reflow (260C, 30s) while achieving MRAM cell size scaling and a low power MRAM. The circuits described below exploits the thermal factor (retention determinant) of the MTJ (magnetic tunnel junction) dependence on the MTJ diameter. Larger MTJ diameters lead to higher thermal factor and so it's easy to pass the solder reflow thermal cycle and maintain data integrity. The larger diameter MTJ has some drawbacks for the system, large write currents (especially at cold) leading to large access transistor widths so the MRAM macro energy specifications for write is not as compelling. The other process option is to thicken the free layer of the MTJ, which makes write speeds slower and hence once again not as great a write energy specification. The proposed array architecture creates an integrated MRAM cell with 2 MTJs, larger diameter for factory data that is to survive the solder reflow and a scaled diameter one for regular use cases in the field. The scaled MTJ has lower write currents and has a Kelvin measure of the MTJ voltage (useful in both read and write conditions). The key feature of this architecture is that the scaled MTJ will be exempt from the solder reflow data retention requirement and only has to satisfy write/read across PVT corners and associated data retention and cycling specs.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 28% of the total text.

Page 01 of 6

Array Architecture to Mitigate Solder Reflow data loss in MRAM

A new array architecture is described to mitigate the tough requirement to ensure data integrity after a solder reflow (260C, 30s) while achieving MRAM cell size scaling and a low power MRAM.

The circuits described below exploits the thermal factor (retention determinant) of the MTJ (magnetic tunnel junction) dependence on the MTJ diameter. Larger MTJ diameters lead to higher thermal factor and so it's easy to pass the solder reflow thermal cycle and maintain data integrity. The larger diameter MTJ has some drawbacks for the system, large write currents (especially at cold) leading to large access transistor widths so the MRAM macro energy specifications for write is not as compelling. The other process option is to thicken the free layer of the MTJ, which makes write speeds slower and hence once again not as great a write energy specification. The proposed array architecture creates an integrated MRAM cell with 2 MTJs, larger diameter for factory data that is to survive the solder reflow and a scaled diameter one for regular use cases in the field. The scaled MTJ has lower write currents and has a Kelvin measure of the MTJ voltage (useful in both read and write conditions).

The key feature of this architecture is that the scaled MTJ will be exempt from the solder reflow data retention requirement and only has to satisfy write/read across PVT corners and associated data retention and cycling specs.

Background

     MRAMs are the future non-volatile memories replacing flash memories. Advantages of MRAM technology is the incremental process steps on top of the logic process (with minimal impact to logic circuits and IP) could be used to embed the MRAM with IP existing on the base logic process. MRAMs provide system specification advantages of low energy writes, scaled macro sizes and fast write performance and considerably high cycling limit for writes.

     MRAMs are challenged in terms of retention of data at elevated temperatures. The large activation energy makes the problem worse for any thermal excursion (even short of the 1min) to high temperatures. The associated data loss at high temperature is particularly of concern during the final manufacturing steps of the circuit board, known as solder reflow (lead free solder reflow worst case per reflow: 260C, 30s). The MRAM data stored in the factory are in jeopardy with the solder reflow step. The usual process mitigation schemes include making the MTJ free layer volume increase (both thicker and larger diameter). The consequence of larger diameter MTJ is the large write currents, increase in cell size due to large access transistor widths (cold write is the worst case at low Vdd). The thicker free layer slows the write speed as well. So the process optimization leads to a higher write energy cell and macro.

     Circuit and testing solutions to the solder reflow data loss include larger ECC overhead, multiple copy of data and associ...