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VLSI/FPGA Method for Testing Data Compression and Data Encryption Logic

IP.com Disclosure Number: IPCOM000246062D
Publication Date: 2016-Apr-29
Document File: 3 page(s) / 56K

Publishing Venue

The IP.com Prior Art Database

Abstract

The purpose of this document is to describe a method of effectively testing data compression and data encryption logic. The testing can be accomplished using and FPGA or in an actual VLSI module where the logic resides.

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Page 01 of 3

VLSI/FPGA Method for Testing Data Compression and Data Encryption Logic

Background:

When designing a new logic macro, simulation is performed to ensure the reliability of the hardware. However, because simulation is very slow relative to hardware, only a very small fraction of input data patterns can be simulated. Data compression and data encryption algorithms both have basically infinite combinations of input data to create a compressed or encrypted data stream. Therefore the overall confidence level in the new macro is not very high and the final verification will take place during initial testing of the module. Considering that it costs close to a half million dollars to manufacture a VLSI module, a designer would ideally like to simulate the new macro in hardware prior to fabrication. The hardware simulation will allow many terabytes of simulation to be performed prior to module release. The same logic that is used in an FPGA prior to releasing the module may also be used in the final module to provide a built in self test of the complicated logic.

Summary:

To sufficiently simulate a new encryption or data compression macro it is desirable to perform the simulations in hardware. The design can be tested using an FPGA or other programmable logic device. However, the simulation will only be as worthwhile as the data input. The designer must be able to provide random data inputs that target different areas of the design and be able to switch between these random inputs easily and quickly in hardware. There are multiple ways to input the test data. The data could come from the user's PC, either a test file or a software random data generator. Random data generation can also be built into the hardware. Multiple hardware modules can be designed to generate data that stress different aspects of the data compression or encryption logic. This method can test terabytes of input data. One challenge of hardware simulation is to be able to recreate a simulation failure in software so that the logic may be analyzed and fixed. The hardware will need registers that store important information, like the record length or initial starting value. This same hardware simulation can be used after the module has been fabricated. This built in self test could be initiated by microcode during idle times of the hardware or during a power on test.

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Description:

The following figure outlines the environment for hardware testing the data compression and encryption macros. There are five elements: the PC, the Rabbit card, the microprocessor interface, the data generators, and the data compression and encryption logic.

Data Compression / Encryption Hardware Model

Data G eneration -- Source 1
-- Source 2
-- Source 3

MUX

M

U X

Rabbit Card

 MP Interface

  Data Compression Encryption

Socket

(Data read from External File or Created On-The-Fly using Data Generation Software on PC)

The PC interfaces with a Rabbit card via Ethernet connection using a C pr...