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Compressive Strained Vertical Transistor by Bottom Silicide Expansion

IP.com Disclosure Number: IPCOM000246074D
Publication Date: 2016-May-03
Document File: 4 page(s) / 165K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method and structure for forming strained vertical positive Field Effect Transistor (pFET) structures by bottom silicide expansion.

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Compressive Strained Vertical Transistor by Bottom Silicide Expansion

The Vertical Field Effect Transistor (VFET) is a device option beyond 7nm node. Channel strain has been an important performance enhancement element for prior nodes and is needed in vertical transistor structures, especially for Silicon Germanium (SiGe) positive Field Effect Transistors (pFETs).

The novel contribution is a method and structure for forming strained vertical pFET structures by bottom silicide expansion.

The following figures represent the process flow for implementing the method in a preferred embodiment.

Figure 1: Start with a Silicon (Si) substrate having a doped well layer, and then epitaxially grow Silicon Boron/Silicon Germanium/Silicon Boron (Si:B/SiGe/Si:B) and an undoped Si device layer.

Figure 2: Form VFETs with source/drain (S/D), spacers, and gate

Figure 3: Deposit silicon nitride (SiN) liner, and Oxide fill (Inter Layer Dialectric)/Chemical Mechanical Planarization (CMP)

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Figure 4: Use a mask to create a trench reaching SiGe, and then perform endpoint Reactive Ion Etching (RIE) until a Ge signal is produced. A Nitride liner protects the devices.

Figure 5: Remove mask and then selectively etch SiGe to create a cavity

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Figure 6: Atomic Layer Deposition (ALD) deposit contact metal

Figure 7: Silicidation anneal: designed metal thickness reacts with the doped semiconductor layer, forming silicide with a 2.2x volume expansion. This closes the ga...