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Method and Structure for Forming CMOS with Reduced Contact Resistance

IP.com Disclosure Number: IPCOM000246075D
Publication Date: 2016-May-03
Document File: 5 page(s) / 81K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a flow and unique structure for providing a sacrificial layer fill in the source/drain (S/D) trench.

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This is the abbreviated version, containing approximately 91% of the total text.

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Method and Structure for Forming CMOS with Reduced Contact Resistance

The current process for forming Complementary Metal Oxide Semiconductors is:

1. Negative Field Effect Transistor (nFET) liner deposit into both nFET and positive Field Effect Transistor (pFET) source/drain (S/D) region

2. Block nFET S/D, and remove linear in pFET S/D region 3. Remove mask and deposit pFET linear; pFET linear will pinch off in nFET to have higher contact resistance

However, linear is only needed at the S/D trench bottom, sidewall linear limits Tungsten fill into S/D to have low resistance. A method is needed to resolve the issues of facilitating dual contact liners and facilitating the chamfering dual liner.

Figure 1: Problem statement

Figure 2: Solution area

The novel solution is a flow and unique structure for providing a sacrificial layer fill in the S/D trench.

Figure 3: Current vs. solution

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The following figures illustrate the process flow in a preferred embodiment.

Figure 4: Incoming in contact region

Figure 5: Contact Oxide etch

Figure 6: nFET Titanium/Titanium Nitride (Ti/TiN) liner deposition at both nFET and pFET region

Figure 7: Sacrificial layer (amorphous carbon (aC)) fill

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Figure 8: Mask to protect nFET region

Figure 9: aC removal from pFET S/D region

Figure 10: nFET linear removal in pFET region and mask removal

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Figure 11: pFet NiPtTi linear deposition

Figure 12: Sacrificial layer (aC) fill

Figure 13: aC recess

Figure 1...