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Method for Enabling Controlled VTFET Gate Recess

IP.com Disclosure Number: IPCOM000246088D
Publication Date: 2016-May-04
Document File: 2 page(s) / 44K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to incorporate a Tungsten hardmask on the Fin structure that enables an end-point mechanism, to significantly improve Tungsten recess depth control in Vertical Tunnel Field Effect Transistor (VTFET) technology.

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Method for Enabling Controlled VTFET Gate Recess

Current Vertical Tunnel Field Effect Transistor (VTFET) technology requires a timed Tungsten gate recess process that proceeds with a great deal of potential variation. This can cause a lack of control in the gate recess depth and consequently gate length concerns.

The novel contribution is a method to incorporate a Tungsten hardmask on the Fin structure that enables an end-point mechanism, which can significantly improve Tungsten recess depth control. Enabling Tungsten hard mask endpointing enables accounting for tooling drifts (i.e., decreased etch rate over tool kit lifetime). This also facilitates a well-controlled over etch process.

The novel process flow follows and is illustrated in the figures below:

1. Form mandrel, deposit spacer 2. Spacer etch back 3. Mandrel pull 4. Form Fin hard mask (HM)

5. Form Fins 6. Deposit and recess bottom spacer, then deposit HiK/work function metal (WFM) 7. Deposit Tungsten 8. Chemical Mechanical Planarization (CMP) polish and stop on WFM 9. Perform Reactive Ion Etching (RIE) breakthrough, and etch down Tungsten, endpoint when hard mask disappears 10. Continue etching as over etch based on initial endpoint. This enables accommodating tool drifts, height changes, etc.

Figure 1: Steps 1-3

Figure 2: Step 4

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Figure 3: Steps 5 and 6

Figure 4: Steps 7-10, Novel VTFET Tungsten Recess

The current VTFET Tungsten recess process has no awareness of tool drift/etch rate var...