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TSV Via Last from Wafer Device Side

IP.com Disclosure Number: IPCOM000246144D
Publication Date: 2016-May-11
Document File: 3 page(s) / 130K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to make Through Silicon Vias (TSVs) that allow the wafer to be processed at full strength (without TSVs) until the end of the processing, which in turn reduces the breakage rate. The approach is to make TSVs after the Back-End-of-Line (BEOL) process, which allows the TSVs to fully land on the backside metal.

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Title

TSV Via Last from Wafer Device Side

Abstract

Disclosed is a method to make Through Silicon Vias (TSVs) that allow the wafer to be processed at full strength (without TSVs) until the end of the processing, which in turn reduces the breakage rate. The approach is to make TSVs after the Back-End-of-Line (BEOL) process, which allows the TSVs to fully land on the backside metal.

Problem

Etching of thru silicon vias post device formation and prior to device wiring levels leaves the wafer in a weakened state. This weakened wafer is then subjected several dep, etch, and polish operations that may cause it to break. Wafers breaking in process tools causes a significant impact to tool availability, spare parts, and cleanliness.

Figure 1: Typical fracture strength behavior

Solution/Novel Contribution

The novel contribution is a method to make Through Silicon Vias (TSVs) that allow the wafer to be processed at full strength (without TSVs) until the end of the processing, which in turn reduces the breakage rate. The approach is to make TSVs after the Back- End-of-Line (BEOL) process, which allows the TSVs to fully land on the backside metal.

Method/Process

The steps for implementing the solution follow:

1. Process the wafer through Middle-of-Line (MOL)/BEOL, except for the last wire level or redistribution layer (RDL), leaving areas for the TSVs to be added later.

2. Flip and mount the wafer on a silicon carrier or similar support structure

3. Process through Backside...