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SYSTEM AND METHOD OF USING POWER RAIL SEQUENCING FOR ENABLING HIDDEN FEATURES WITHIN A COMMERCIALLY AVAILABLE ASIC

IP.com Disclosure Number: IPCOM000246187D
Publication Date: 2016-May-13
Document File: 6 page(s) / 116K

Publishing Venue

The IP.com Prior Art Database

Abstract

System and method for using power rail sequencing for enabling hidden features within a commercially available application specific integrated circuit (ASIC) are disclosed. The system and method are configured to adding specific voltage levels and timing for providing multiple patterns of power rail sequencing at each power up cycle, through changes to circuitry both internal and external to the ASIC. By sequencing the power up between two or more analog rails after the logic supply is stable, multiple bit patterns are generated. These patterns combined with the clock and digital input/output signals can control a state machine that provides access to the hidden features. Any customized pattern of voltages and timing can be used to be used to protect an ASIC. This allows the producer of the part to recover the design costs from open market sales, while reducing the cost to licensed users compared to a fully customized development.

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SYSTEM AND METHOD OF USING POWER RAIL SEQUENCING FOR ENABLING HIDDEN FEATURES WITHIN A COMMERCIALLY AVAILABLE ASIC

BACKGROUND

The invention relates to application specific integrated circuits (ASICs) and in particular to a system and method for using power rail sequencing for enabling hidden features within a commercially available ASIC or part. The development of mixed signal ASICs requires large engineering cost to support the design efforts. For commercially available off-the-shelf (COTS) parts, manufacturers will pay back this cost over the sales of the ASIC or part while custom parts for a single user require the cost to be paid prior to the delivery of the parts. Use of the COTS parts keeps product development cost low, yet the hardware will easily be matched by other companies using the same COTS parts.

FIG. 1 shows a typical mixed signal part with analog and digital circuits within an ASIC under control of a processor. Power supplies to the overall device are under control of a power sequencer to ensure correct power up operation. The internal ASIC features are controlled via signals from the control, where these may be parallel or serial paths. The simplest way to signal a change in behavior is by sequencing of supply rails, where a specific pattern of which is first or last (input/output pins) triggers the hidden feature. The hidden features may be detected using various forms of invasive and non-invasive tests. Invasive tests expose the part die for examination and direct probing of internal nodes, while non-invasive tests use various forms of attack such as side- channel attack, software attacks and fault generation. All of these use the known input/output pins on the part for detecting the hidden features. When the part becomes a mixed signal design, including analog circuitry, the attack is much more complex given that signals no longer are binary. Such an attack using invasive tests, removal of part packaging to allow probing of the internals will enable reverse engineering of the component. The proposed method uses power rails instead of using the input/output pins of the mixed signal part, in a way that prevents reverse engineering.

 


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FIG. 1: Typical mixed signal part with analog and digital circuits within an ASIC

This disclosure shows a method to allow a part to be available as a COTS product, while providing a way to enable additional features for specific users. This allows market features to be available while blocking others access to these features and allowing the development costs to be paid by COTS sales to other users.

BRIEF DESCRIPTION OF DRAWINGS

The invention discloses system and method for using power rail sequencing for enabling hidden features within a commercially available application specific integrated circuits, wherein:

Fig.1 shows a typical mixed signal part with analog and digital circuits within an ASIC under control of a processor.

Fig.2 shows a modified mixed signal...