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Chip intrinsic metric aware core-granular workload scheduling and management to improve reliability

IP.com Disclosure Number: IPCOM000246361D
Publication Date: 2016-Jun-02
Document File: 3 page(s) / 96K

Publishing Venue

The IP.com Prior Art Database

Abstract

The Disclosed method is to leverage the core intrinsic attributes and runtime chip/system level metrics to generate suitable “vital” data variable set (runtime metrics convoluted over vital product data (VPD) data) in an multi-core processor environemnt. This method will allow the chip to expose these metrics to various system level stack components including, but not limited to On-chip controller (OCC), hypervisor, Operating System (OS) scheduler. Components leverage “vital” data set using suitable runtime algorithms to optimize one or more parameters such as power/performance/temperature/reliability of the entire server system.

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Chip intrinsic metric aware core-granular workload scheduling and management to improve reliability

Background & Problem Statement:

In virtualized and cloud computing environments, virtual machines may lock up processor cores for significant amount of time, in which case, the usage and therefore degradation is a function of how workloads are hosted and executed by Virtual machines (VM) for the runtime duration: Exposing core usage statistics and leveraging core intrinsic metrics by Hypervisor would open numerous ways to ensure fairness of core(s) usage and degradation among pool of virtual machines Hypervisor allocates resources to virtual machines using logical Central Processing Unit (CPU) internally mapped to physical CPUs, however mapping is done mainly on physical attributes. Considering the above limitations, drawbacks and opportunities, therefore a novel approach and method is needed to improve chip reliability/power/performance/temperature by leveraging chip intrinsic attributes coupled with run time statistics

Summary

In a multi-core chip, the invention proposes to leverage core intrinsic attributes plus run-time chip/system level metrics to generate suitable "vital" data variable set (runtime metrics convoluted over Vital Product Data (VPD); Expose these metrics to various system level stack components including, but not limited to On-chip controller (OCC), hypervisor, Operating System (OS) scheduler.Components leverage "vital" data set using suitable runtime algorithms to optimize one or more of the following: power/performance/temperature/reliability

In this context, "intrinsic attributes" refers to combination of

metrics due to process variation in the manufacturing process

measured margins/parameters in tester

parameters out of design analysis + simulation

Implementation:

Method #1:

Ø In a multi-core chip, extract measured parameters of each core in manufacturing floor, covering but not limited to the following: Vmin, Fmax, Burn in metrics like End of Life (EOL) degradation. Lets say, dataset C{m}

Ø Attribute physical location and related intrinsic metrics, covering but not limited to the following: IR drop from power header, noise floor, di/dt noise, temperature. Lets say, dataset C{i}

Ø Abstract C{m}, C{i} and classify/rank each core based on various grade parameters (say

C{g}) of interest

Ø During system runtime, track utilization of each core using one or more or combinative, including but not limited to the below. Les say, dataset C{r}

Ø Cycle per instructions (CPI) stack met...