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Dynamic I/O Width Scaling for Memory Power Management

IP.com Disclosure Number: IPCOM000246465D
Publication Date: 2016-Jun-09
Document File: 2 page(s) / 40K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is dynamic I/O width scaling for memory power management.

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This is the abbreviated version, containing approximately 100% of the total text.

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Dynamic I/

/O Width Scaling for Memory Power Management

O Width Scaling for Memory Power Management

Memory power is growing, and its I/O power is taking many portions of them. As memory bandwidth also grows, its interface is going to high-speed serial type of interface, where the link (I/O) needs to be always turned on because its turn-on time takes a very long time once it is turned off. Changing to a different frequency is not doable as the changing speed is so slow too. This make I/O power efficiency poor because the memory has to consume the same power even if its memory demand is low from time to time, and it could have saved lot of power if the I/O power could be adjusted as a function of bandwidth.

    So far, focus has been made only to power of each I/O. As the overall power is # of I/O times power per I/O, if the # of I/O can be reduced in lower bandwidth mode, then it can save a lot of power, and transition between different modes can be done very fast because voltage and frequency of each I/O would not change. The invention also shows that for 64b data + 8b CRC (or ECC), this scheme does not leave any waste of a bit in the packet (72 = 8*9 = 6*12 = 4*18 = 3*24 = 2*36).

    Figure 1 depicts a block diagram for this invention. Figure 2 depicts a timing diagram for this invention. Figure 3 depicts a timing diagram showing the conventional method for throttling.

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