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Window Detector

IP.com Disclosure Number: IPCOM000246511D
Publication Date: 2016-Jun-14
Document File: 1 page(s) / 35K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is a window detector circuit.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 93% of the total text.

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Window Detector

To make sure that only relevant data from Iout is accepted, window detector circuit has been implemented in the phase redundant regulator circuit. Window detector circuit was added to specify a range of acceptable voltage levels so that when the master receives the Iout signal, its value can be compared within this defined range. If outside this range, then value is ignored.

The phase redundant regulators implemented in this circuit use voltage mode control. Current sense output signal called Iout on the slave sends data back to the master (in volts) - this is called current reporting. Based on this data, the master adjusts the PWM, thereby modifying the output voltage. The PWM is adjusted because of the requirement of balancing the circuit. If the current sense data sent to the master is contaminated, the output voltage will be incorrectly modified.

In order to make sure that only relevant data from Iout is accepted, window detector circuit has been implemented.

Window detector circuit was added to specify a range of acceptable voltage levels, so that when the master receives the Iout signal its value can be compared within this defined range. If the current feedback signal is outside of this normal operating range then this signal ignored and the phase is disabled, otherwise the PWM is modified and output voltage is adjusted.

The figure below shows a block diagram of this circuit where ISEN and IRTN are current sense inputs on the master. Sense...