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TSV Stress Monitor Structures in Interposers

IP.com Disclosure Number: IPCOM000246630D
Publication Date: 2016-Jun-23
Document File: 1 page(s) / 56K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses the piezoelectric property of the silicon substrate in the through silicon via (TSV) to sense stress.

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TSV Stress Monitor Structures in Interposers

Monitoring through silicon via (TSV) related stress is a common problem. In Complimentary Metal-Oxide Semiconductor (CMOS) chips, the Field Effect Transistors (FETs) can be used as stress monitors. Typically, three-dimensional (3D) interposers do not contain FETs; therefore, so a structure that can electrically monitor TSV stress is needed.

In interposers, without FETs there are no good options other than optical (i.e., spectroscopic) or X-ray based techniques. Current techniques involve expensive de-layering and are destructive.

The novel method uses the piezoelectric property of the silicon substrate to sense stress. Two crisscross resistors are measured in a fixed proximity to the TSV.

Additionally, multiple versions at different distances can be used to obtain an accurate value of stress.

This method enables the measurement of TSV stress in proximity electrically. It is non-destructive and is easily integrated into products.

Figure: Process flow in a preferred embodiment

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