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Nanosheet Schottky Transistor

IP.com Disclosure Number: IPCOM000246682D
Publication Date: 2016-Jun-27
Document File: 5 page(s) / 96K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a novel structure and method for a Nanosheet Schottky Transistor.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 92% of the total text.

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Nanosheet Schottky Transistor

Nanosheet is one option for future Complementary Metal Oxide (CMOS) technology nodes. Scaling makes the structures denser and progressively reduces the contact space, which increases integration challenges such as self-aligned contact (SAC),

junction formation, and contact resistance. The Schottky Barrier Transistor helps with

junction and contact resistance because everything is metal, except the channel.

Presented herein is a novel structure and method for a Nanosheet Schottky Transistor. The following figures represent the components and process for building the Nanosheet Schottky Transistor.

Figure 1: Form nanosheet stack; alternating Silicon Germanium/Silicon (SiGe/Si layers)

Figure 2: Form dummy gate and thick gate spacer

Figure 3: Recess source drain

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Figure 4: Recess SiGe and form inner spacer (Process on Record (POR), known art)

Figure 5: Recess Si

Figure 6: Deposit Atomic Layer Deposition (ALD) gold (Au) liner (positive Field Effect

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Transistor (pFET)) or ALD Erbium (Er) liner (negative Field Effect Transistor (nFET)), followed by an ALD silver layer to protect Erbium from oxidation (Au/Er are Schottky contact metals, making ohmic contacts). Then fill with contact metal, Chemical Mechanical Planarization (CMP) back to gate top hardmask.

Figure 7: Recess metal

Figure 8: Recess metal

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Figure 9: Form contact trench

Figure 10: Fill with contact metal

Figure 11: POC, the poly-open step,...