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BARE FIBER ATTACHMENT TO SILICON PHOTONIC CHIP

IP.com Disclosure Number: IPCOM000246840D
Publication Date: 2016-Jul-06
Document File: 7 page(s) / 781K

Publishing Venue

The IP.com Prior Art Database

Abstract

In various exemplary embodiments, the present disclosure provides mechanisms for bare fiber attachment to Silicon Photonic (SiPhot) chips which supports thinner wafers while concurrently providing sufficient mechanical strength for the fiber attachments. The present disclosure uses deep-trench layers in CMOS fabrication to perform edge coupling. Advantageously, the present disclosure eliminates the need for a ferrule/optical subassembly, i.e., there is only a need to strip and cleave the optical fibers. This approach is compatible with wafer back-side thinning for high density electrical/optical assemblies. Further, this approach requires no special optical facet preparation or extra steps.

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BARE FIBER ATTACHMENT TO SILICON PHOTONIC CHIP

ABSTRACT


[0001]In various exemplary embodiments, the present disclosure provides mechanisms for bare fiber attachment to Silicon Photonic (SiPhot) chips which supports thinner wafers while concurrently providing sufficient mechanical strength for the fiber attachments. The present disclosure uses deep-trench layers in CMOS fabrication to perform edge coupling. Advantageously, the present disclosure eliminates the need for a ferrule/optical subassembly, i.e., there is only a need to strip and cleave the optical fibers. This approach is compatible with wafer back-side thinning for high density electrical/optical assemblies. Further, this approach requires no special optical facet preparation or extra steps.

BACKGROUND


[0002]In order to couple light from an optical fiber to a silicon photonic (SiPhot) chip containing sub-micron sizes strip waveguides, two general coupling approaches are used. The first one uses grating couplers and the second one is edge coupling including inverted tapers and Multi-rod structure spot-size converters (MRS-SSC) [such as described in US Patent Publication No. 2015/0247974]. The following FIG. 1 illustrates one example of the edge coupling approach with inverted tapers:

FIG. 1. Block diagram of an edge coupling approach with inverted tapers


[0003]For a typical packaged optical component, the optical fiber mechanical attachment to the SiPhot chip has to sustain a mechanical pull of 500 gr. In order to fulfill this requirement, the fiber is typically mounted in a ferrule in order to increase the contact surface (and attachment strength) in-between the fiber and the SiPhot chip.

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[0004]A new trend in SiPhot chip development is to introduce a wafer back-side thinning in order to facilitate the 3D integration of chips for electrical/optical compact functionalities which can include Through Silicon Vias (TSV). The SiPhot chip can be thinned from about 750 m to about 100-200 m, which is not compatible with the use of a ferrule fiber in edge coupling configuration and the stack up in a compact manner of a layer underneath since the ferrule has a much wider diameter than the remnant SiPhot chip thickness. The use of a ferrule in edge coupling configurations with a regular SiPhot chip and one that is thinned is illustrated in the following FIG. 2.

FIG. 2. Block diagram of use of a ferrule in edge coupling configurations with a regular SiPhot chip (top) and one that is thinned (bottom)


[0005]A deep-trench process is used in a Complementary metal-oxide-semiconductor (CMOS) fab, such as IME, in order to etch the surface vertically by about a hundred microns. It allows the SiPhot chip facet preparation in order to perform edge coupling. The SiPhot die is then delimited by a rectangular deep-trench shape in order to manage optical inputs and outputs. After die dicing, bare fibers can be used to inject light in/out the optical circuits. A...