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Structure for reducing thermal runaway in inverters

IP.com Disclosure Number: IPCOM000247049D
Publication Date: 2016-Jul-29
Document File: 5 page(s) / 304K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a layout designed to limit overstress runaway outcomes in inverters, without significant impact to performance. The solution is a buffer layout modification to introduce a "ballasting" resistor for first stage Field Effect Transistors (FETs).

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Title

Structure for reducing thermal runaway in inverters

Abstract

Disclosed is a layout designed to limit overstress runaway outcomes in inverters, without significant impact to performance. The solution is a buffer layout modification to introduce a "ballasting" resistor for first stage Field Effect Transistors (FETs).

Problem

Burn-in requires acceleration of failure modes by accelerated voltage and temperature conditions applied at the chip level. Under such conditions, some Field Effect Transistors (FETs) become overstressed, due to device self-heating. This sometimes results in thermal runaway. Large FETs are most susceptible due to both high finger density and the capability of opposing FET to feed high current to the nominally off-state FET.

Existing solutions may add resistance in circuits, which has a higher impact to performance. Other technology solutions are not compatible with the isolation required for performance or reduced variability.

Solution/Novel Contribution

The novel contribution is a layout designed to limit overstress runaway outcomes, without significant impact to performance. The solution is a buffer layout modification to introduce a "ballasting" resistor for first stage FETs.

The core idea is for an Inverter, Nand, or Nor design in which the negative FET (NFET) portion of a driving stage is connected to the next stage through a wiring that is separate from the positive FET (PFET) portion of the same driving stage.

Method/Process

When...