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Die Local Power Dissipation Reduction Technique Targeting Chip Partition With Reduced Activity

IP.com Disclosure Number: IPCOM000247077D
Publication Date: 2016-Aug-02
Document File: 2 page(s) / 38K

Publishing Venue

The IP.com Prior Art Database

Abstract

Described is a die local power dissipation reduction technique targeting chip partition with reduced activity.

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This is the abbreviated version, containing approximately 50% of the total text.

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Die Local Power Dissipation Reduction Technique Targeting Chip Partition With Reduced Activity

Power dissipation continues to be the largest issue facing integrated circuit products today, particularly in mobile applications. A large number of local power gating techniques have been developed to mitigate total chip power dissipation, but they generally require chip units to be completely powered on or off. This invention allows for a reduced supply voltage inside a chip partition affording a large reduction in total chip power.

    This invention enhances the classic power gating technique to reduce power consumption when activity inside a given power island (subset of the integrated circuit) is sufficiently low. The low switching activity reduces the power supplies drops, reduces the local temperature, and reduces signal noise effects that are detrimental to performance. The new technique involves a reduction in the width of the power gating structure, nominally a PFET header to increase the impedance between the power supply(s) and the functional unit's circuits, greatly reducing the power dissipation.

    As mentioned above, the gating of a subset of the power supply gating device structure, in this example a very wide PFET header with as small of total impedance as is afforded by area limitation, is desired to limit the supply voltage and, therefore, the power dissipation of the die partition that is experiencing limited activity. Operating applications allow very accurate switch factor assertions and would allow this technique to be utilized in all customer environments, saving power in all applications.

    For the sake of illustration, assume a typical 5% switching factor; i.e., 5% of the potentially switchable capacitance is switched each clock cycle during normal, high activity operation. The targeted, under-utilized functional unit switch factor is nominally <1%, let us assume 0.5% for the calculations here. Additionally, assume the Tj raise will be nominally 50C in the heavily used units (5% sf) and perhaps 5C in the under-used unit(s). Typical IR drops of ~60mV are nominally asserted for heavy activity die subsets so one could calculate ~6mV with low activity units, assuming the full-width header is designed to maintain that same 60mV drop at the specified 5% switch factor.

    If one assumes a 1V nominal supply voltage, the reduced Tj allows only about 2% more performance for typical paths with nominal wire and via resistance components and transistor threshold response to reduced temperature. More importantly, the reduced IR drops coupled with this reduced Tj allow the circuit voltages to be dropped approximately 80mV on a typical 1V nominal supply while preserving frequency. The drop in the header device itself is typically on the order of 20mV; i.e., it's 1/3 of the total power supply drop from the regulation point to the circuit loads. One can reduce the width of the device by 80% in this example and reduce the circuit voltage b...