Browse Prior Art Database

Dynamic Hierarchy Overlapping Sub-Flattening Tool

IP.com Disclosure Number: IPCOM000247080D
Publication Date: 2016-Aug-02
Document File: 5 page(s) / 206K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for increasing the usage of logic real estate by improving the density factor and reducing the overall power consumption. The approach is to collapse logic from disparate blocks where workloads not simultaneously functioning at in said blocks.

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Title

Dynamic Hierarchy Overlapping Sub-Flattening Tool

Abstract

Disclosed is a method for increasing the usage of logic real estate by improving the density factor and reducing the overall power consumption. The approach is to collapse logic from disparate blocks where workloads not simultaneously functioning at in said blocks.

Problem

Silicon real estate is a scarce resource, and the use duty cycle for usage can be low for a large percentage of the cycle time. As the development of technology nodes advances, the power is shifting from Active to Leakage Power. Therefore, a large portion of unused logic is causing significant power usage with no work gained.

Current art keeps logic cones unique and separate, has no means of tracking mutually exclusive cones, and synthesizes the cones as separate identities.

Solution/Novel Contribution

The novel solution is a method for increasing the usage of logic real estate by improving the density factor and reducing the overall power consumption. The approach is to collapse logic from disparate blocks where workloads not simultaneously functioning at in said blocks.

Method/Process

The novel solution uses a score-boarding technique to mark logic cones that are mutually exclusive in the time domain perspective. The technique includes multi- methods such as clock tree gating trace back and simulation score-boarding a Register Transfer Logic (RTL) netlist to build a scoreboard.

A first run thru of gate netlist is created via conventional means. An analysis of common gate use and timing budget analysis creates a list of potential gate sharing cones. The technique adds a front end cone sharing logic and then creates common logic cone sharing, such that a portion of the original design shares gates based upon the score boarding exclusivity function. As such, an overall reduction of gates occurs, reducing standby current of unused gates and overall chip die area, reducing both cost and improving power budgets.

The novel method and structure comprise:


• A method of marking NETLIST cones that are non-overlapping

• The scoreboard tracking time domains of RTL

• Means of inserting shared cones structure via incremental physical synthesis
• Means of sharing generated shared logic cones

The resulting reduced gate structure maintains the Boolean equivalent to the original non-overlapping logic structure.


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Comparison of Process Flows

Process on Record:


1. RTL

2. Synthesis

3. Place/route/timing

Solution Embodiment:

1. RTL

2. Score-boarding through simulation and clock domain analysis 3. Synthesis

4. Gate analysis/common gate identification

5. Score-boarding ranking/finding the most number of common nodes/twigs/branches


6. Insertion of mux/sharing structure into Netlist


7. Place/Route/Timing

Figure 1: Shared Logic Structure

Referring to Figure 1, the system is composed of multiple independent clock domains: A, B, …, G. The diagram depicts only one shared circuit; in general, each logic pat...