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Integrated Plasma Doping and Metal Gate Scheme to Enable Multi-Vt for Highly Scaled FinFET CMOS Replacement Gate

IP.com Disclosure Number: IPCOM000247117D
Publication Date: 2016-Aug-08
Document File: 6 page(s) / 215K

Publishing Venue

The IP.com Prior Art Database

Abstract

This disclosure describes how to integrate plasma doing and metal gate patterning to implement the multi-Vt in the replace metal gate scheme for Highly Scaled FinFET CMOS. Here the plasma can be done with cold platen or hot platen.

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Integrated Plasma Doping and Metal Gate Scheme to Enable Multi - Scaled FinFET CMOS Replacement Gate

Highly scaled CMOS is desirable for performance improvement or save the power consumption. However, highly scaled CMOS faces the very high challenges to tune the threshold voltage(Vt) by using channel doping due to very thin or ultra-thin body. Very high channel doping is possible to tune the threshold voltage in some degrees. But the mobility degradation is associated with very channel doping. So the device with very high channel doping suffers the performance degradation. Therefore, the work function of the gate metals is prefered to use to set or tune the Vt for highly scaled CMOS.

In addition, in replacement metal gate, the device feature is quite small for highly scaled CMOS due to performance improvement requirement. Therefore, it is quite difficult to offer more than two Vts for nfet and pfet because the device feature can only allow the limited gate metal patterning if no zero thickness work function patterning is used. Plasma doping of gate metals is one of zero thickness work function patternings to change the work function of gate metals and then change the Vt. In this disclosure, we describe how to integrate plasma doing and metal gate patterning to implement the multi-Vt in the replace metal gate scheme for Highly Scaled FinFET CMOS.

Our experiments suggest that N plasma implantation with heated platen can modulate the Vt with ToxGL and mobility impr...