Browse Prior Art Database

Method to Improve ISOVIA Chain Yield by Using SiARC Film as a Via Memorization Mask

IP.com Disclosure Number: IPCOM000247211D
Publication Date: 2016-Aug-17
Document File: 2 page(s) / 354K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to improve isolated via chain (ISOVIA) yield and reduce defects by replacing Low Temperature Oxide (LTO) with Silicon-containing Anti-Reflective Coating (SiARC).

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Method to Improve ISOVIA Chain Yield by Using SiARC Film as a Via Memorization Mask

Low Temperature Oxide (LTO) film on the Organic Dielectric Layer (ODL) is defective
(i.e., embedded and surface defectivity). Titanium Nitride (TiN) Physical Vapor Deposition (PVD) on LTO creates additional defectivity, with many defects. These defects cause severe degradation in via chain yields.

Figure 1: Illustration of the problem

Figure 2: Photo Limited Yield (PLY) post-LTO/TiN deposition

Figure 3: PLY Post R1 Hardmask Over etch (HMO)- Defectivity

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The proposed solution is a method to replace LTO with Silicon-containing

Anti-Reflective Coating (SiARC) (17% to 43%). The approach includes a new film stack (ODL/SiARC/TiN) for via Litho. Alternate films, such as Silicon Carbonitride (SiCN), Silicon Nitride (SiN), and Silicon Oxynitride (SiON) can also be used in place of SiARC

Figure 4: Result - TiN deposition on SiARC

SiARC on ODL is a stronger interface and will not have any defects in the film (i.e., no defectivity with ODL/SiARC/TiN scheme). SiARC film can withstand up to 350C (TiN deposition) and has better compatibility than LTO in via wet clean (300:1 HF). It does not cause critical dimension (CD) increase. TiN and SiARC can be wet-removed for any easy rework. This solution is cost effective and reduces processing time.

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