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Standard Cell Libraries for 3D Monolithic Silicon Technology

IP.com Disclosure Number: IPCOM000247243D
Publication Date: 2016-Aug-17
Document File: 4 page(s) / 170K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method for a 3D monolithic Silicon process to allow transistors to be stacked in a 3D configuration on a single wafer is disclosed.

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This is the abbreviated version, containing approximately 37% of the total text.

Page 01 of 4

Standard Cell Libraries for 3D Monolithic Silicon Technology

Disclosed is a method for a 3D monolithic Silicon process to allow transistors to be stacked in a 3D configuration on a single wafer. Current standard cell design uses the same cell design for both bottom transistors and top transistors without any regards for interconnecting between top and bottom designs. This approach causes issues with connecting the bottom circuits to the top circuits and requires either top or bottom cell to be depopulated to allow space for the connections between the bottom and top circuits. This article discusses novel methods of designing standard cell library circuits to realize the potential density benefits of the technology. Built-in inter-connections for the upper and lower designs are proposed to allow space inside the cell designs. Additional

circuit specific optimization's related to this are discussed. Figure 1 depicts a cross section of the 3D monolithic technology with field-effect transistor (FET) entries.

Figure 1

The disclosed method is to utilize built-in inter-connections for the upper and lower designs to allow space inside the cell designs to avoid or minimize depopulation for upper to lower inter-connections. The inter-connections can be pre-designed or programmable depending on the design methodology. Library designed circuits are further optimized to take advantage of the 3-D monolithic technology to maximize

wireability and other circuit performance improvements.

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The Standard Cell layout design is implemented by having a fixed height and width. Such as 12 metal1 tracks high and Nx1 metal1 track width. The height of the cell is a function of the chip performance requirement. Larger cell height can be used for higher performance designs and smaller cell height can be used for lower performance designs. In a given cell design, there is a row of inter-connection pads along the bottom or the top of the cell to allow inter-connections between the circuit layers. Additionally, the bottom layer can be designed with two separate Standard Cell libraries. One

without the inter-tier connections for usage within the bottom layer and one with the inter-tier connections for 3D inter-connections with the top layer. This approach maximizes both performance and density. Figure 2 depicts a standard cell design. Figure 3 depicts an extra track at the top of the cell to enable inter-tier routing and/or an extra track to enable power rail sharing. An equivalent design would have the extra

track at the bottom of the cell. Figure 4 depicts an extra track at the top and the bottom to allow for more inter-tier routing.

Figure 4

Figure 2

Figure 3

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Figure 5

Figure 5 depicts an example with the reserved track on the right side. Similar designs could be on the left side or both sides. Figure 6 depicts a combination of the top and right side. Figure 7 depicts an example where each side has a reserved track.

Additional 3D mo...