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Vertical Ferroelectric Field Effect Transistor

IP.com Disclosure Number: IPCOM000247281D
Publication Date: 2016-Aug-18
Document File: 5 page(s) / 133K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a channel-last replacement metal-gate gate all-around vertical transistor flow as a method of co-integration of ferroelectric field effect transistors (FETs) alongside traditional vertical FETs.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 67% of the total text.

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Vertical Ferroelectric Field Effect Transistor

Vertical transistors are an attractive option for technology scaling for 5nm and beyond. Ferroelectric gates can be used as an option to provide sub-60mV/decade subthreshold slope transistors. Co-integration of ferroelectric field effect transistors (FETs) alongside traditional vertical FETs would be critical in achieving a viable hybrid technology.

The solution proposed herein is a channel-last replacement metal-gate gate all-around vertical transistor flow.

To implement the solution, a ferroelectric material is deposited between the gate electrode and the channel material, with only simple modifications to the channel-last replacement metal gate (RMG) vertical transistor flow.

An additional embodiment includes a metal layer between the High-K dielectric and the

ferroelectric material.

The following figures represent the steps for implementing the vertical ferroelectric field effect transistor in a preferred embodiment. All views are cross-sections.

Figure 1: Form deep source drain (S/D), blanket bottom spacer, the top oxide

Figure 2: Etch channel region, grow oxide on dummy gate using plasma oxidation

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Figure 3: Channel epitaxy, recess, nitride deposition, and chemical mechanical planarization (CMP)

Figure 4: Drain epitaxy and sidewall spacer formation, pull dummy gate, remove oxide - everything up to this point is prior art

Figure 5: Ferroelectric material deposition, CMP, and reactive ion etching (...