Browse Prior Art Database

Structure and Method to Retain Strain in Strained SiGE Planar FDSOI FETs

IP.com Disclosure Number: IPCOM000247403D
Publication Date: 2016-Sep-01
Document File: 6 page(s) / 113K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed are a new method and structure to reduce/eliminate the relaxation effect after shallow trench isolation (STI) formation and Silicon Nitride (SiN)/pad oxide strip.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 53% of the total text.

Page 01 of 6

Structure and Method to Retain Strain in Strained SiGE Planar FDSOI FETs

In Fully Depleted Silicon on Insulators (FDSOI), strained channel Silicon Germanium (cSiGe) is a key performance enabler for a positive Field Effect Transistors (PFET). However, after the shallow trench isolation (STI) formation and the Silicon Nitride (SiN)/pad oxide strip, the edge of the cSiGe at the active area starts to relax, which can have a negative impact on the PFET if the active width perpendicular to gate is not large. As the device continues to scale, the width is continually decreases. The relaxation is becomes increasingly evident.

Figure 1: Schematic of the issue

Proposed herein are a new method and structure to reduce/eliminate the relaxation effect. By using this approach, the cSiGe is always coated by SiO2/SiN hardmask combination to maintain the lattice and does not relax. Before the cSiGe top surface is exposed, a dummy gate structure is formed at the RX edge to prevent the cSiGe relaxation.

STEP 1

A. Start from FDSOI wafer (the top Si is 5 to 12nm)

B. Deposit SiO2/SiN as hardmask (HM). Litho to open PFET region and remove SiO2/SiN.

C. Convert the PFET region from Si to strained SiGe by SiGe EPI and condensation


D. Strip all HM


E. Re-deposit SiO2 (~3nm) + SiN (~10nm) + SiO2 (~5nm) + SiN (200 to 400nm)

(this is different from the conventional stack, which has 2 layers using SiO2 (3 to 5nm) and SiN (200 to 400nm)

Figure 2: Step 1

1


Page 02 of 6

STEP 2

A. Litho to open STI area B. Deep STI etch into Si substrate (the SiGe top surface is still sealed by SiO2/SiN/SiO2/SiN, it will not relax)


C. Fill STI with SiO2 and CMP to stop on top SiN

Figure 3: Step 2

ST...