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A High Performance Voltage Level Translator with Integrated Multiplexer

IP.com Disclosure Number: IPCOM000247423D
Publication Date: 2016-Sep-06
Document File: 3 page(s) / 58K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a high performance voltage level translator design for reducing logic contention and improving latency between voltage level translations. The voltage level translator design has an enable signal embedded into it which allows the level translator to be used as a multiplexer under multiplexing conditions.

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Page 01 of 3

A High Performance Voltage Level Translator with Integrated Multiplexer

    Multiple supply voltages are commonly used in designs to enable better power-performance through improved control on the supply voltage for the various functional units. In multiple supply voltage designs, circuits are partitioned into voltage islands which operate at their optimum supply voltages. The use of multiple supply voltage islands require voltage level translators between them. Described is a high performance voltage level translator topology for high frequency operation.

The conventional voltage level translator shown in Fig. 1 uses two supply voltages VDD and VCS.

Figure 1: Conventional Voltage Level Translator


The PMOS transistors (T0 and T1) and (T2 and T3) act as a cross-coupled load. When the input signal IN is low (logic 0),

NMOS transistor T4 is turned 'ON' and provides a conducting path to ground while NMOS transistor T5 is turned 'OFF' and PMOS transistor T3 is turned 'ON'. Therefore node 'NODE_B' is pulled down to ground which makes PMOS transistor T2 'ON'; due to which node 'NODE_A' is pulled high (logic 1) to VCS. Thus, the output signal OUT becomes low. The operation reverses when the input signal IN is switched to high. This conventional voltage level translator has large delay because it suffers from contention between the pull-down transistors (T4 and T5) and the pull-up transistors (T0, T1, T2 and T3). The presence of complex gates and stacked transistors also adds to the increased latency. This article describes an approach in which the contention is reduced, and also the number of complex gates and stacked transistors are reduced from the input to the output to gain better performance in delay.

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Page 02 of 3

    An approach is described here to reduce the contention, and decrease the number of complex gates and stacked transistors along the input to output path. The voltage level translator shown in Fig. 2 has an integrated enable signal which acts as a signal to control the functioning of the level translator. EN='1', ENN='0' and ENN_VDD='0' for the proper functioning of the level translator.

Figure 2. Proposed Voltage Level Translator

    
The key idea to reduce the contention is to pull one of the contention node to a known voltage, instead of leaving it at an undefined state. As shown in Fig. 2, the LVT transistor T5 whose gate is connected to input signal IN is the key transistor in reducing the rising delay between IN and OUT nodes. Assuming that initi...