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Automatic Frequency Scaling PCIe Free-Running Timer

IP.com Disclosure Number: IPCOM000247432D
Publication Date: 2016-Sep-07
Document File: 1 page(s) / 43K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a design for an automatic frequency scaling Peripheral Component Interconnect Express (PCIe) free-running timer. The novel design allows the link speed to change at-will, without affecting the timeout real-time value.

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Automatic Frequency Scaling PCIe Free-Running Timer

Peripheral Component Interconnect Express (PCIe) protocol specifies completion timer durations in real time, but the protocol requires hardware to run with variable clock frequencies, making a fixed cycle count assignment impractical. In some systems, PCIe timers run at Peripheral Clock (PCLK) frequency, which changes based on trained

link speed (e.g., Gen 1 = 125MHz, Gen2 = 250MHz, Gen3 = 500MHz). PCIe timeout values can be configurable and specified in actual time durations, for instance: 10us, 4ms, 16ms, 64ms, 256ms, 1s, 4s, 32s. Because time is tracked in cycles, timers/timeouts need to be adjusted to match different frequencies.

A free-running timer increments by one at a fixed time rate, regardless of clock frequency. Logic uses a gearbox function to scale down the timer update frequency based on a trained link speed. The system can force an update by one every 8ns (i.e., 1x 125 MHz cycle).

The novel design allows the link speed to change at-will, without affecting the timeout

real-time value. All timeout ranges specified by PCIe are a single hard-coded value based on the configuration selected in PCIe config space. Multiple transaction timers
(64) can be run via a single free-running 36-bit auto-scaling timer plus 64x 2-bit

wrap-state indicators to significantly reduce latch count.

The timer can be scaled in a fixed time scale with the gearbox function selecting the current link speed from the timer using...