Browse Prior Art Database

Timing Aware Advanced Retargeting

IP.com Disclosure Number: IPCOM000247649D
Publication Date: 2016-Sep-22
Document File: 5 page(s) / 137K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for exploiting timing margins on physical wires that are a part of timing paths in order to provide additional space for fine-grained retargeting.

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Page 01 of 5

Title

Timing Aware Advanced Retargeting

Abstract

Disclosed is a method for exploiting timing margins on physical wires that are a part of timing paths in order to provide additional space for fine-grained retargeting.

Problem

Retargeting involves modifying feature shapes for improved manufacturability. For lower technology nodes, retargeting/pattern optimization needs additional flexibility to fix potential issues.

The current method of pattern correction is restrictive with resistive-capacitive (RC) delay pseudo-unchanged/minimal constraint imposed.

One known solution is to perform timing analysis and slack margin determination for every path during static/statistical timing analysis. Another solution includes coupling capacitance information (with neighboring wires) as part of timing analysis of all paths.

Solution/Novel Contribution

The novel contribution is a method for exploiting timing margins on physical wires that are a part of timing paths in order to provide additional space for fine-grained retargeting, which is not allowed by current method flows.

The novel method of timing aware retargeting includes annotating the slack margin of timed paths to wired segments of the respective path and incrementally retargeting the segments of path based on the annotated slack margin property. The allowed additional margin for the retargeting operation is added as property of segments in the database. The grid based retargeting can be performed using annotated information from the wired segments.

The method adds grid optimization property to segments and vias of database through:

1. Performing path based timing analysis of wired database

2. Incrementally changing the width to alter the resistance and capacitance of segments, the segments part of tied path

3. Calculating the new value of RC delay through the path

4. Determining the maximum allowed width change in any segment in any part of if there is fail in timing for the relevant path

5. Converting the maximum allowed width change to grid optimization points post referencing the metal width dimensions

6. Adding the grid optimization point as a common property for all segments of a particular timed path.

Method/Process


Page 02 of 5

Figure 1: Method flow for data preparation

Additional steps for the method flow for data preparation include:

1. Timing tool determines the "maximum value" of resistance, and capacitance can be altered in the wire segments/vias of a particular timed path without failing timing for that respective path. This is done on the basis of incremental RC delay increase/decrease, which causes a timing failure for that path; every segment of a timed path is individually and separately altered until there is timing fail. This provides the maximum allowed width modification for each segment. The least value amongst all the segments for a particular timing path is selected. This defines the maximum allowed width modification f...