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Embedded Capacitive Sensor Array for CPI (Chip-Packaging Interaction) Package Reliability Monitoring

IP.com Disclosure Number: IPCOM000247656D
Publication Date: 2016-Sep-23
Document File: 5 page(s) / 156K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is an embedded capacitive sensor array for Chip-Packaging Interaction (CPI) package reliability monitoring. The solution not only monitors early failures, but also provides understanding of the rate, propagation, and severity of cracking in real time.

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Title

Embedded Capacitive Sensor Array for CPI (Chip-Packaging Interaction) Package Reliability Monitoring

Abstract

Disclosed is an embedded capacitive sensor array for Chip-Packaging Interaction (CPI) package reliability monitoring. The solution not only monitors early failures, but also provides understanding of the rate, propagation, and severity of cracking in real time.

Problem

Mechanical failures are a common occurrence within the interconnections of a flip-chip package. Failures are often induced due to the composite (layered/mixed) structure within the package and mismatch in mechanical properties, especially coefficient of thermal expansion (CTE) of the various zones. One such type of failure is observed at the solder interconnections (or C4s) where the CTE mismatch between the silicon die and the organic substrate leads to failure in those joints.

One of the biggest challenges in microelectronics flip-chip packaging is managing/mitigating the chip-packaging interaction (CPI) stresses that occur due to the coefficient of thermal expansion (CTE) mismatch between the silicon chip (~3 ppm) and the organic laminate carriers (~17 ppm). The CTE mismatch between chip and substrate creates increased mechanical stress that is highest in the chip corners (as Figure 1). Encapsulating the solder joints with underfill increases the life-cycles, but does not completely eliminate the possibility of breakage in electrical connection. The underfill material is subjected to high mechanical stresses in the package leading to development of bulk and interfacial cracks, which propagate solder interconnections and cause failure.

Figure 1: Increase mechanical stresses in the corner region of the chip

The increased mechanical stress at the corners of the chip in turn drives crack propagation from the lower chip corner in three main regions: underfill sidewall delamination, bulk underfill cracking, and underfill to chip delamination underneath the chip (Figure 2).


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Figure 2: Main crack propagation routes in the flip chip organic module: 1) Underfill sidewall delamination 2) bulk underfill cracking 3) underfill to chip delamination

Underfill sidewall delamination and bulk underfill cracking damage the mechanical integrity of the module, but do not directly hamper the module electrical performance. Crack propagation underneath the chip ultimately terminates in the C4 or chip metallurgy, thereby severing the electrical pathways and causing module failure.

Figure 3: C-SAM of the underfill. Delamination can be seen in the upper left corner, but is difficult to identify due to the poor resolution of the technique.

Figure 4: Extensive under chip module damage in failed part as seen by ultra-violet (UV) microscopy of a cross section


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During product qualification, stringent accelerated reliability tests are performed to project the field condition life-cycle for a specific package. However, the established reliability techniques a...