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Method and Structure for High Strained SiGe FinFET Device beyond 7nm Node

IP.com Disclosure Number: IPCOM000247698D
Publication Date: 2016-Sep-28
Document File: 7 page(s) / 266K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is an integration process flow for adding new stressors during the PC cut last process without adding extra masks and involving minimal process steps. This is meant to reduce stressor/stress to ensure continuous scaling during strain technology processes.

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Method and Structure for High Strained SiGe FinFET Device beyond 7nm Node

Strain technology is a key enabler for improving transistor performance; however, experts in the art do not know whether stressors maintain effectiveness with continued reduction in stressor volume, as transistor pitch scales and whether stressors will be recovered after Fin cut.

Approaches to have strain in the devices include:
 Source/drain (S/D) epitaxy: Silicon Germanium (SiGe) for positive channel metal-oxide semiconductor (PMOS) and Silicon Carbon (Si:C) for negative channel metal-oxide semiconductor (NMOS)


 Gate metal fill, which wraps around the fin (e.g., Titanium Nitride (TiN) fill)


 Metal fill for the trench contact (e.g., Tungsten (W))


 Shallow Trench Isolation (STI) fill

Traditionally, SiGe has been used as a stressor for PMOS extensively on S/D. SiGe Fin has stress reduction after Fin cut. This significantly impacts performance because most of the performance of SiGe is from channel stress, and integration
of small pitch or trench leaves very little room for additional stressors. Aggressive scaling requires narrow gates and Fin pitch, which makes adding a large amount of stressors difficult.

Figure 1: Problem summary

A method is needed to address the reduction of stressor/stress to ensure continuous scaling.

The novel contribution is an integration process flow for adding new stressors during the PC cut last process without adding extra masks and involving minimal p...