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Si Epi Layer for Protecting Sensitive Fins During Fabrication

IP.com Disclosure Number: IPCOM000247699D
Publication Date: 2016-Sep-28
Document File: 2 page(s) / 54K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to apply a silicon epitaxy (Si epi) layer for protecting sensitive fins during fabrication. The method grows an Si Cap epi layer (1-2 nm) post Fin Etch clean or post Fin Reveal for Silicon (Si), Silicon Germanium (SiGe), Germanium (Ge) or III-V fins; the Si Cap layer protects fin during integration processing.

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Si Epi Layer for Protecting Sensitive Fins During Fabrication

Fins made from Silicon Germanium (SiGe) (high Ge), pure Ge, and III-V materials, which are highly sensitive to wet processing. Severe Fin erosion happens during the processing steps and limits the use of conventional chemistries.

Figure 1: Illustration of the problem

The proposed idea is to grow an Si Cap epi layer (1-2 nm) post Fin Etch clean or post Fin Reveal for Si, SiGe, Ge, or III-V fins. The Si Cap layer protects fin during integration processing. The process optimizes the thickness of the Si cap layer for any loss during processing.

For the Si Cap Epi layer growth for both positive and negative Field Effect Transistors (PFET and NFET), the process grows the Si Epi as a capping film post-Fin Etch or post-Fin Reveal to protect SiGe, Ge, and III-V Fins.

Figure 2: Si Cap Epi layer growth for both PFET and NFET

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Figure 3: Selective Si cap Epi layer growth for only NFET in Block mask approach

This solution is applicable for Silicon on Insulator (SOI), Bulk, or Strained Silicon on Insulator (SSOI). The approach can selectively cap Si Epi SiGe/Ge/ III-V fins with an Si epi cap layer using Block masks or along with Si Fins. Liner nitride is not needed for Si Fin if a block mask is used. For SiGe or Ge case, thermal mixing can be performed at the end of the Fin definition, to intermix the Si cap epi layer with the fins.

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