Method of Building a Resistance Network for Transistor’s Gate
Publication Date: 2016-Sep-28
The IP.com Prior Art Database
We describe a method that eliminate a negative resistance value in a triangular gate resistance network.
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Method of Building a Resistance Network for Transistor's Gate
To enable representing the gate resistance in a SPICE netlist for any of three layout cases shown in Fig. 1, a triangular
gate resistance network has been used (see Fig. 2). Previous gate resistance netlisting includes
horizontal gate resistance component only. This results the value of r_b being always negative.
Fig. 1. Three layouts that represent gate contact at one end of PC (gate) only (Ngcon = 1), at the other end of PC only (also Ngcon = 1), at both ends of PC (Ngcon = 2).
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Fig. 2. A triangular resistive network for the gate node of a transistor.
Recent study shows that, besides the horizontal gate resistance component, there is also a vertical gate resistance component. After including the vertical gate resistance component,
the values of gate resistance for various cases are the following:
a. One of two PC ends is connected to outside
b. Both PC ends are connected to outside
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c. DC conduction between the two "external" nodes
where L is the transistor's channel length, W is the transistor's channel width, r_sh is the sheet resistance of the gate, r_v is the vertical resistance per unit area (in the unit of ohm-m^2), and d_rx2cnt is the distance between a pair of diffusion and contact boundaries.
We eliminate the negative resistance value (in rb ) in the triangle gate resistance network by including the vertical gate resistance component and using the follow...