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Semiconductor Device with Selective Back-Gate Bias Capability

IP.com Disclosure Number: IPCOM000247703D
Publication Date: 2016-Sep-28
Document File: 3 page(s) / 36K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a Silicon on Insulator (SOI) structure with circuits shielded from an applied back-gating bias by junction isolation.

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Semiconductor Device with Selective Back -Gate Bias Capability

In some circumstances, applying a common bulk bias to simultaneously modulate the threshold voltage of both positive and negative Field Effect Transistors (nFETs and pFETs) is advantageous. However, this approach is neither uniformly applicable for all operating modes, nor advantageous for all devices. In one manifestation, the bulk bias is negative, to simultaneously reduce the magnitude of the pFET threshold voltage while increasing that of the nFET. Not all circuits should be subject to the backgating bias needed for performance in some implementations of Extremely Thin Silicon on Insulator (ETSOI).

The novel contribution is a method by which to form regions that the backgate bias cannot modulate. The design is a Silicon on Insulator (SOI) structure with circuits shielded from an applied back-gating bias by junction isolation. The core idea is to insert junctions below the buried oxide (BOX) to provide separate regions that the backgate bias does not affect. This disclosure illustrates how some regions of the design may be electrically isolated from the bulk bias, so that the detrimental effects of changing the bias may be avoided, while retaining the advantageous effects in the other circuits.

The regions of the chip to be so isolated might be:


 Static Random Access Memory (SRAM) arrays that need to retain logic state in sleep mode when the bulk bias generator may be disabled


 Thick oxide d...