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Self-Assembled Punch-through Stopper in VFET Transistor

IP.com Disclosure Number: IPCOM000247736D
Publication Date: 2016-Oct-03
Document File: 5 page(s) / 93K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a self-assembled punch-through stopper (PTS) underneath the vertical Fins for suppressing the subsequent drain dopant diffusion to substrate, as well as subVt lkg.

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Self-

Different from traditional Fin Field Effect Transistor (FinFET) devices, a vertical FET (VFET) has a transport channel in a horizontal direction. This creates challenges to achieve uniform ext junction formation from vertical fin top to bottom and restrain the punch-through lkg and subthreshold lkg in the bottom drain/fin bottom/substrate region.

A punch-through stopper (PTS) was typically done by angle implants and may become impracticable (ground rule restriction) on neighboring VFET devices in ultra-scaled Complementary Metal-Oxide Semiconductor (CMOS) technology. A method is needed to fabricate PTS on a VFET device without damaging the vertical channel and bottom drain materials.

The novel contribution is a self-assembled PTS underneath the vertical Fins for suppressing the subsequent drain dopant diffusion to substrate, as well as subVt lkg. The novel structure uses a dummy Silicon Germanium (SiGe) buffer layer, stack films deposition, high selective dry etch on buffer layer release, and carbon doped dielectric refill to form the PTS layer. The novel process flow is for fabrication PTS on a VFET device (i.e., steps 1, 4, 6, 7, 8 in the process flow).

Figure 1: Structure of VTFET device with PTS

The following figures (i.e., 2-15, labeled as Steps) illustrate the process flow in a preferred embodiment.

Step 1: Incoming structure SiN/Si fin/SiGe/substrate

Step 2: Fin Patterning and Reactive Ion Etch (RIE)

-Assembled Punch

Assembled Punch - -through Stopp...