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Wafer scale gate array

IP.com Disclosure Number: IPCOM000247745D
Publication Date: 2016-Oct-04
Document File: 4 page(s) / 35K

Publishing Venue

The IP.com Prior Art Database

Abstract

Achieve system connectivity at the wafer level by designing & fabricating connections between microelectronic circuit reticle fields, using wiring on the same semiconductor wafer as the circuits for the logic computation and memory storage.

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This is the abbreviated version, containing approximately 51% of the total text.

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Wafer scale gate array

Computer systems have been integrated using diced chips with xy dimensions limited to less than 30 mm in each direction. For these chips to communicate with others chips, they have traditionally needed to go through interconnects which have at least a 150 um

pitch; limiting the density of the communication. Thru silicon vias used in 3D technology enable dense z direction connectivity. However, this does not alleviate the limitations in xy direction connectivity. Silicon interposers increase xy connectivity, but still require additional interconnects & an extra level of assembly. This invention provides a reticle field interconnection scheme which enables a system to be designed & built within a wafer.

A submitted IBM disclosure called "Architecture and Implementation of Cortical System using 3D Wafer Scale Integration" describes a neuromorphic system architecture which is one type of application which can benefit from this Wafer Scale Gate Array (WSGA) IP. The present disclosure and this referenced disclosure can have a symbiotic effect in that the WSGA disclosure can enable the Architecture disclosure, while the Architecture disclosure can make the WSGA disclosure more valuable.

This publication explains how to achieve system connectivity at the wafer level by designing & fabricating connections between microelectronic circuit reticle fields, using wiring on the same semiconductor wafer as the circuits for the logic computation and memory storage. The removal of the under 30x30 mm area restriction allows wiring connections, which previously required a

package or interposer, to now be incorporated into the wafer. Plus it greatly increases the density of xy connections, since the invention will allow wiring to be done on center to center pitches on the order of 2 um, without needing to go through much coarser interconnects: thus leading to increased circuit integration, which increases performance & throughput. This invention providesa structure which enables a gate array to connect circuits in different reticle fields.

Wafer scale gate array

A gate array uses a set of fixed layers which remain the same between multiple designs, plus a small number of personalized layers to customize the interconnection.

Previously, this concept was limited to personalizing connections within a reticle field, for which tooling generally limits the expose field and integrated circuit (IC) x dimension (Cx) and y dimension (Cy) to under approximately 30 mm. This invention provides a structure which enables a gate array to connect circuits in different reticle fields.

The structure in this invention includes the following:

1


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2 to n IC fields on the same wafer which are to be interconnected within the...