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Transient Response Characterization of Semiconductor Wearout Characteristics

IP.com Disclosure Number: IPCOM000247748D
Publication Date: 2016-Oct-05
Document File: 3 page(s) / 25K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to monitor wear in-situ for the purpose of workload allocation and as a field reliability early-warning monitor for high performance systems.

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Transient Response Characterization of Semiconductor Wearout Characteristics

This solution is relevant to the fields of electrical test, semiconductor reliability, and intermittent/marginal failure characterization and wear-leveling. Specifically, multi-core high-throughput processors invariably experience asymmetrical workloads on the individual processor cores. For example, typically one core will run the operating system, using only integer arithmetic logic unit (ALU) IP blocks and very little else, whereas a core tasked with simulations would heavily tax floating point hardware, and another core tasked with transaction processing would be very cache intensive. Over time, this leads to asymmetrical wear along signal pathways resulting in non-uniform changes to core performance.

A class of soft defects exists that escape time zero test and grow with runtime in the field. Currently, the first indication of fail tends to be product fails while running in the field. Using the existing mechanisms for generating transient signals within the chip, transient response monitoring is a methodology that increases the detection rate and enables ongoing monitoring of this class of soft defects.

The goal of the novel solution is to monitor wear in-situ for the purpose of workload allocation and as a field reliability early-warning monitor for high performance systems.

Upon core power-up or transition to another voltage-frequency corner, or opening/closing of a gated clock network, a bounce occurs in the power and clock signal nets. Analysis of the product response to this input stimulus provides information to enable ongoing monitoring of changes to the clock or power nets. Changes of the observed response to the input pulse are indicative of changes to the net itself, which may be due to device shifting due to wear and tear from operation, or progression of AC latent defects and other degradation faults.

This is advantageous in that it is a direct monitor of structures of interest rather than a test site analog, requires minimal additional hardware overhead, and takes advantage of commonly occurring sequences of events to extract diagnostic information. Cores are routinely powered up, powered down, and run at dynamic frequencies and voltages depending on the current workload demands. Upon core power up, transition to another voltage-frequency corner, or opening/closing of a gated clock network, a bounce in the power and clock signal nets occurs. This bounce, which is typically considered a problem, provides resonant characterization of the signal net. Changes to this spectral signature are indicative of changes to the net itself, essentially the wear and tear from operation, and can monitor the presence and progression of AC latent defects and other degradation faults (e.g., metal migration, resistive-leaky shorts, resistive opens, increased capacitance, etc.)

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In the majority of mainframe applications, cores are used asymmetr...