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Novel algorithm for scan insertion

IP.com Disclosure Number: IPCOM000247804D
Publication Date: 2016-Oct-06
Document File: 7 page(s) / 87K

Publishing Venue

The IP.com Prior Art Database

Abstract

Background: Shrinking technology with increase in design density and increase in operational frequency has posed serious design and test challenges. Structural qualification of the design after manufacturing an IC is critical. Test / fault Coverage which determines the Shipped product quality level (SPQL) without increasing the test time is the need of the hour and plays a part in overall design budget/cost. . ATPG patterns are proven techniques to detect different types of structural defects. ATPG is used to detect manufacturing defects by supplying patterns through ATE, ATPG is performed by configuring the entire flops / LSSD’s in the design into shift registers of several chains, and these chains are then initialized by ATE in every pattern. After shifting a pattern in to the design, Device is configured into Scan-capture mode and the shifted values of the flop propagate through the functional path and coverage for specific type of defect is evaluated. In order to reduce test time, various techniques of compression – decompression are being widely adopted in the industry, Where codec’s ( compressor – decompressor), de-compress the ATE driven pattern into several large chain’s and feed into the chains, decompressor’s decode / merges the signatures from the chains and pushes the signatures out of the chip and drives ATE. The values driven into the ATE are compared with pre-established values generated by ATPG tool. Almost all of the architectures of compression-decompression suffer from the problem of correlation (Unable to attain expected values during end of scan-shift) in codec mode. Problem definition: Various ATPG tools generate ATPG patterns to target different types of defects. Patterns count increases with increase of complexity, size of the design and decreased nanometer sizes. With increase in types of defects, various types of patterns are also generated to comprehend the defect types. These increases test time, test volume and its generation time even in codec mode, Codec mode suffers predominantly to achieve the expected coverage or would inflate patterns because, ATPG tool often encounters care bit conflict where in the tool cannot achieve intended values on the required flops / LSSD latches post scan shifting, These care bit conflicts are often seen due to non care-full placement position of scan flops during scan stitching by the scan insertion / scan-stitching tools. This disclosure, discloses an efficient method / algorithm and a flow to stitch scan flops to satiate this issue, by which when implemented a better coverage could be achieved by limited number of patterns. Proposed solution: This disclosure involves, a systematic method and an algorithm to identify scan flops / LSSD latches (which are very critical care bits in pattern generation process) that often determine the achieved coverage and the cause for pattern count inflation, positioning them in different internal scan chains/stumps either during scan insertion / scan stitching process or during scan chain re-ordering which eliminate the care bit conflicts. Identifying Hard to detect faults attributing to control care bits always in codec mode by any method (Manual or automated form like ATPG) which have always a dependency on some finite circuit values to test. Proposed solution comprises an algorithm to find the list of scan flops which are part of above specified control logic cones, and algorithmically placing them in a smart way such that they would avoid care bit conflicts, i.e. distributing these care bit flops in different scan chains so that the ATPG tool can easily control them with required values, there by avoiding care bit conflicts, henceforth minimizing the effort of the tool and reducing the pattern count.

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Novel algorithm for scan insertion

Embodiment1:

Below example in Fig1 showcases an example of Illinois scan architecture, where a scan-in port directly drives multiple scan stumps based on fan-out factor. This also depicts the scenario, where when the care bit locations are placed in different stumps driven by same scan-in port parallel to each other, Faults may not get covered by the ATPG tool or might become a very hard to detect fault because of the correlation effect (pattern which needs the colored 2 sets of 2 flops to have different value but would not be able to attain the same after scan shifting). A similar problem would be applicable for any other type of scan-decompression technique.

The Proposed method / algorithm involves firstly identifying the critical care bits while scan stitching and secondly placing them strategically at locations such that the care bit conflicts in codec or compression mode is minimized / avoided.

The identification of critical care bits (scan able Flip-Flops / LSSD) might be by,

1. A logic cone analysis/identification method, which could be by identifying the flops / LSSD that control the control logic of (clock / data / reset / power gating control pins of LSSD / Flip-flop) thru the combinational cone that root causes to loss of coverage / increases pattern count.

Examples of identifying critical care bits (Flip-flops / LSSD) can be one or a combination of


 Identifying the flops / LSSD latches that control / gate the clock thru ICG (integrated clock gate) in functional / scan capture mode. This set of identified care bits could be further analyzed by engineering algorithms so that further filtering of flops can be attained which would have higher care bit dominance.


 Identifying the flops that control Asynchronous /Synchronous, set/reset logic of a Latch / LSSD to make the flops be in set or reset state during sc...