Browse Prior Art Database

Bounded Latency Zone in Flash-Only Storage Systems

IP.com Disclosure Number: IPCOM000247897D
Publication Date: 2016-Oct-10
Document File: 7 page(s) / 228K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a technique to allow a portion of a flash-only storage system’s capacity to respond to read operations with bounded latency, avoiding the variance typically associated with such operations.

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Bounded Latency Zone in Flash-Only Storage Systems

Existing low-latency solutions in flash-based storage systems involve the use of non-flash storage within the overall storage system. Figure 1 illustrates the limitations of the existing art.

Figure 1: Behavior and drawbacks that result from existing art


a) Write input/output (I/O) operation request arrives


b) Write I/O operation conducted to cache and considered complete

1


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c) Resource contention in region 1 caused while cache contents are de-staged. Arriving read request to region 1 is queued.


d) Write operation complete, relieving contention to region 1. Read operation can be executed.


e) All I/O operations complete

2


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A method is needed that offers the bounded latency feature without requiring additional tiers of storage within the system.

The novel contribution is a technique to allow a portion of a flash-only storage system's capacity to respond to read operations with bounded latency, avoiding the variance typically associated with such operations.

A flash-only storage system provides only one place to store information: in the physical pages of individual flash memory devices. The novel technique provides bounded latency at the flash level by mapping each bounded latency logical page address to two physical addresses that reside in different regions within the storage system. It schedules host writes and garbage collection writes and erases in a way that always leaves one region available for immediate read access/rapid response.

The typical flash device is organized such that the physical package contains multiple individual flash dice. Each die is organized into some number of planes . Each plane contains some number of blocks . The block is the unit of erase operations in a flash device. Each block contains some number of physical pages . The physical page is the unit of read/write operations in a flash device.

Each plane has associate access circuitry that implements the logic required to carry out operations on blocks and pages

within the plane. Each die within a device can execute arbitrary operations in parallel. The planes within a die can carry out parallel operations, but only if both of the die's planes are executing the same operation (i.e., read, write, or erase). Further discussion of this capability is outside the scope of this disclosure.

Garbage collection in flash storage systems is necessitated by the unit size for erase operations (i.e., the block) is larger than the unit size for read and write operations i.e., (the physical page). Consequently, the process must migrate remaining valid data out of a block to a new location in order to make the block available for erasure and re-use.

The variance normally associated with read and write operations in flash storage systems arises from contention for the access circuitry associated with the planes/dice. When an operation requires the use of access circuitry that is already busy ser...