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Flip Chip PoP with Copper Carrier Interposer Etched to form Copper Pad

IP.com Disclosure Number: IPCOM000247963D
Publication Date: 2016-Oct-14
Document File: 8 page(s) / 588K

Publishing Venue

The IP.com Prior Art Database

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Flip Chip PoP with Copper Carrier Interposer Etched to form Copper Pad

Background

Semiconductor devices are widely used in modern electronic products. One goal of semiconductor manufacturing is to produce smaller devices with high-density packages used in various products such as mobile phone, PDA and digital camera. In the traditional packaging technology, discrete IC packages are placed directly on the PCB side-by-side. In contrast, Package-on-Package (PoP) is an IC packaging method combining the vertical integration of IC packages. The solder balls on the bottom surface of the top package are soldered onto the contact pads on the top surface of the bottom package, providing z-axis interconnection for the stacked packages. The PoP technology offers shorter routing of interconnections between circuits, resulting in faster signal propagation and reduced noise and cross-talk. In the PoP technology, the packages can be tested separately before being assembled. This method has the advantage over the stacked-die technology in which the entire assemble is useless since there is no chance of choosing "known good die" (KDG).

Fig. 1 Conventional Flip Chip Package-on-Package (PoP) Multi Level Package (fcPoP-MLP) structure

In Fig. 1, one example of the conventional Flip Chip Package-on-Package (PoP) Multi Level Package (fcPoP-MLP) structure is shown. The solder balls on the top surface of the bottom package, the solder balls on the bottom surface of the top package, and the interconnect between the top and bottom packages provide electrically conductive pathways and mechanically supports to the assemblies. In order to produce reliable interconnects, laser ablation is used to create holes for the top solder balls before the packages are stacked. In Fig. 1, a die is located on the laminate substrate in a flip chip style and encapsulated in the bottom package. The bottom package can further be mounted to PCB in the BGA method through the solder balls below the laminate substrate. A substrate interposer is also shown as a structural component in the example. A top package or multi packages can be stacked on the substrate interposer, and thus electrically and thermally connected through the substrate interposer, the solder balls, the laminate substrate and finally to the PCB.

Together with many benefits, the current PoP assembly technology still has some issues related to the solder ball interconnection between the top and bottom stacked packages. Although the process is cheap for the current PoP method involving laser ablation to create the holes for solder ball interconnects, this method faces the collapse issue, since the soft solder balls are adopted as external pillars. The situation becomes even worse when smaller solder balls are needed when more I/Os are required. To solve the problem, Cu pillars are


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Flip Chip PoP with Copper Carrier Interposer Etched to form Copper Pad

formed in the substrate, instead of solder balls to su...