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Copper Post Interconnection on CCSB for Interposer PoP

IP.com Disclosure Number: IPCOM000247968D
Publication Date: 2016-Oct-14
Document File: 5 page(s) / 492K

Publishing Venue

The IP.com Prior Art Database

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Page 01 of 5

Copper Post Interconnection on CCSB for Interposer PoP

Background

Semiconductor devices are widely used in modern electronic products. One goal of semiconductor manufacturing is to produce smaller devices with high-density packages used in various products such as mobile phone, PDA and digital camera. In the traditional packaging technology, discrete IC packages are placed directly on the printed circuit board (PCB) side-by-side. In contrast, Package-on-Package (PoP) is an IC packaging method combining the vertical integration of IC packages. The solder balls on the bottom surface of the top package are soldered onto the contact pads on the top surface of the bottom package, providing z-axis interconnection for the stacked packages. The PoP technology offers shorter routing of interconnections between circuits, resulting in faster signal propagation and reduced noise and cross-talk.

In Fig. 1, one example of the conventional Flip Chip Package-on-Package (PoP) Multi Level Package (fcPoP-MLP) structure is shown. The solder balls on the top surface of the bottom package, the solder balls on the bottom surface of the top package, and the interconnect between the top and bottom packages provide electrically conductive pathways and mechanically supports to the assemblies. A die is located on the laminate substrate in a flip chip style and encapsulated in the bottom package. The bottom package can further be mounted to PCB in the BGA method through the solder balls below the laminate substrate. A substrate interposer is also shown as a structural component in the example. A top package or multi packages can be stacked on the substrate interposer, and thus electrically and thermally connected through the substrate interposer, the solder balls, the laminate substrate and finally to the PCB.

Fig. 1 A conventional Flip Chip Package-on-Package Multi Level Package (fcPoP-MLP) structure

Together with many benefits, the current PoP assembly technology still has some issues related to the uniform clearance between the interposer and the bottom substrate after the interposer attachment (IA) process. In US8106495B2, a semiconductor apparatus and a manufacturing method thereof are disclosed, more particularly to a resin-sealed semiconductor apparatus in which a semiconductor chip is received between stacked wiring substrates and a gap between the wiring substrates is filled with a resin, and a manufacturing method of the semiconductor apparatus. Therefore, it is possible to obtain sufficient reliability by improving adhesion properties in a semiconductor apparatus of a structure in which a thinned semiconductor chip is mounted between wiring substrates and is sealed with


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Copper Post Interconnection on CCSB for Interposer PoP

a resin. In US8623704B2, an adhesive/spacer structure is used to adhere first and second die to one another at a chosen separation in a multiple-die semiconductor chip package. The first and second dies define a di...