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Interposer-less FI-PoP (Fan-In Package on Package)

IP.com Disclosure Number: IPCOM000247972D
Publication Date: 2016-Oct-14
Document File: 4 page(s) / 424K

Publishing Venue

The IP.com Prior Art Database

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Interposer-less FI-PoP (Fan-In Package on Package)

Background

A common semiconductor device arrangement includes an upper semiconductor package stacked over a lower semiconductor package, i.e. package-on-package (PoP). The upper semiconductor package is typically electrically connected to the lower semiconductor package with solder balls.

A need exists for an interconnect structure for PoP with reduced package height and cost reduction. The patent application numbered US 20140103509 disclosed PoP without an interposer by using conductive ink. The conductive ink is dispensed on the encapsulation and makes circuit pattern, which replaces an interposer to place a top package. But a problem is the conductive ink may be delaminated from the encapsulation because of low adhesion between the conductive ink and the encapsulation.

To solve the problem, the process of grooving an encapsulant is added before dispensing ink. The grooving makes recesses, which provides more contact area surface, which provides higher adhesion than prior art.

Description

Disclosed is a method of forming a grooved pattern surface and conductive ink layer

Fig. 1: Starting point is general bottom PoP package. The package comprises a substrate, a die having bumps, interconnect such as solder ball (top solder ball), and an encapsulant is disposed over the package.

Fig. 2: Via holes are formed by ablation tool such as laser. Many different type of via holes may be provided through control of laser energy and exposure time. Via holes expose the top solder ball.


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Interposer-less FI-PoP (Fan-In Package on Package)

Next step, patterns are grooved in the top surface of encapsulation. The patterns may define circuit traces and terminals (pads) that provide complete interconnection from top solder balls to upper package.

In other embodiment, via holes and pads can be made at once. And then the traces are made. In addition, via holes and the patterns may be formed by single step of laser ablation.

Fig. 3: The conductive ink layer as a package interconnect structure in PoP. Via holes and patterns are filled to provide the interconnect structure. Via holes and patterns may be filled by conductive ink. The conductive ink is dispensed along the recesses made by the grooved patterns.

The conductive ink layer can be formed with one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, Pd, Pt, iridium, osmium, or other suitable electrically conductive material. The conductive ink layer contains powdered or flaked silver, carbon, n-type semiconductor material, or other conductive printable materials using a printing process.

The patterns can be formed with one or more method of inkjet dispensing, screen pri...