Browse Prior Art Database

Low Cost & Thin Profile Interposer Package for PoP Application Disclosure Number: IPCOM000247973D
Publication Date: 2016-Oct-14
Document File: 4 page(s) / 220K

Publishing Venue

The Prior Art Database


This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 51% of the total text.

Page 01 of 4

Low Cost & Thin Profile Interposer Package for PoP Application


A common semiconductor device arrangement includes an upper semiconductor package stacked over a lower semiconductor package, i.e. package-on-package (PoP). The upper semiconductor package is typically electrically connected to the lower semiconductor package with solder ball, copper post, or copper core solder ball (CCSB). A need exists for an interconnect structure for PoP with reduced package height and lower manufacturing cost.

Disclosed is one layer copper based substrate with copper post to replace conventional two layer substrate. The copper post on the interposer is provided, instead of CCSB, to interconnect bottom package with the interposer.

There are several advantages on this invention.

1. Thin profile interposer package can be implemented by etch out of base copper frame.

2. Low interposer substrate cost can be achieved due to very simple & dual panel process.

3. Low cost interposer substrate can be electrically routed freely by finer Line/Space application such as 15/15um.

4. Ni/Au pad finish that protects thermal attack to the ball pads surface of interposer substrate can be plated.

5. Low assembly cost can be realized by applying Molded Underfill (MUF) process and eliminating laser ablation process that required to expose top solder ball.


The following is a method of forming an interposer with copper base frame. There are shown an exemplary side view of the interposer.

Fig. 1: A carrier to provide a support structure for forming the interposer. The carrier includes an inter layer, and copper layer on top and bottom side. The carrier is same with core materials used in coreless substrate. It is usually called 'detachable core'.

Fig. 2 shows the structure in the 1st laminating phase. A photoresist layer is applied on top and bottom side of carrier directly. And then the portion of photoresist is removed to form a pattern mask, respectively.

The photoresist layer is formed from a photosensitive material such as dry film (D/F).

Page 02 of 4

Low Cost & Thin Profile Interposer Package for PoP Application

The photoresist layer can be patterned to form holes. For example, the photoresist layer can be exposed to ultraviolet light through a photomask having a pattern representing the holes. After patterning, the photosensitive layer can be cured to set the photosensitive material and form the pattern mask.

Fig. 3 shows the surface finish to prevent oxidation and diffusion. Usually Ni/Au layer is plated on the part of exposed.

Fig. 4 shows plating phase, which include plating the metal layer directly on the carrier and within the holes of Fig.2. The metal layer is formed from a copper. Forming the metal layer include forming the component attachment pads and the redistribution layer in the holes. Forming a metal layer directly on the carrier provides increased functionalit...