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Alternative PoPb MeP with Embedded active flip chip and Stacked via structure

IP.com Disclosure Number: IPCOM000247975D
Publication Date: 2016-Oct-14
Document File: 6 page(s) / 214K

Publishing Venue

The IP.com Prior Art Database

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Page 01 of 6

Alternative PoPb MeP with Embedded active flip chip and Stacked via structure

Background

Various Package-on-package (PoP) structures have been developed for many applications, such as hand phones and other portable devices in which the circuit board space is limited. In the PoP structure, the top package is typically a memory package whereas the bottom package is a processor package. The PoP technology is more preferred to the stacked-die circuit technology, since different memory packages can be substituted in a PoP circuit. In addition, the top and bottom packages can be tested independently, which lowers down the manufacture cost.

The PoP technology faces a major challenge of reducing the interconnect pitch between the top package and the bottom package. The bus width between the top and the bottom packages increases continuously, but the interconnect pitch between the top and the bottom substrates can only accommodate a certain number of signals. The molded-embedded PoP (MeP) technology has been raised to solve the small-pitch requirement. In the MeP structure shown in Fig. 1, an additional interposer may be included on the bottom package. The additional interposer can redistribute signals to accommodate signals to and from the dies in the top package. In Fig. 1, solder balls are embedded after molding and adopted as interconnects with the bottom portion connected to the laminate substrate and top portion connected to the interposer.

Fig. 1 A Molded-embedded PoP (MeP) structure with a laminate interposer on the bottom package

In the prior art shown in Fig. 2, an alternative MeP package with molded interconnect substrate (MIS) is disclosed. It provides a low cost solution with MIS substrate and enables a fine interconnection pitch of copper pillar by using laser vias and copper filling, instead of solder balls shown in Fig. 1. However, the PoP vertical interconnect usually need a high aspect ratio to cater for a die height. The requirement for interconnects of a high aspect ratio produces many problems such as low throughput, complex process flows, high defect rates and high cost. In Fig. 2, it is difficult to fill the recesses to form copper pillars of such a high aspect ratio In addition, the typical thickness of die is over 100 micron, but delamination and cracking may occur when the via depth exceeds about 80 to 90 micron.

Fig. 2 A Molded-embedded PoP (MeP) structure with molded interconnect substrate (MIS)


Page 02 of 6

Alternative PoPb MeP with Embedded active flip chip and Stacked via structure

Description

This invention discloses a method of manufacturing an alternative MeP with a structure of stacked vias in which two or more shorter vias of a smaller aspect ratio are stacked on each other to form a longer via structure. The aspect ratio for this stacked vias structure can be increased to a desirable value, in order to save space for PoP structure and thus enable an active flipchip die embedded in the package.

This inv...