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Method for eWLB and Flipchip PoP with Routed Leadframe Interposer

IP.com Disclosure Number: IPCOM000247978D
Publication Date: 2016-Oct-14
Document File: 8 page(s) / 909K

Publishing Venue

The IP.com Prior Art Database

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Page 01 of 8

Method for eWLB and Flipchip PoP with Routed Leadframe Interposer

Background

Various Package-on-package (PoP) structures have been developed for many applications, such as hand phones and other portable devices in which the circuit board space is limited. The PoP technology faces a major challenge of reducing the interconnect pitch between the top package and the bottom package. The bus width between the top and the bottom packages increases continuously, but the interconnect pitch between the top and the bottom substrates can only accommodate a certain number of signals. The molded-embedded PoP (MeP) technology has been raised to solve the small-pitch requirement. In the MeP structure shown in Fig. 1, an additional laminate interposer may be included on the bottom package. The additional interposer can redistribute signals to accommodate signals to and from the dies in the top package. In Fig. 1, copper core solder balls (CCSB) are embedded after molding and adopted as interconnects with the bottom portion connected to the laminate substrate and the top portion connected to the laminate interposer.

Fig. 1 A Molded-embedded PoP (MeP) structure with a laminate interposer on the bottom package

The technology of Flip Chip Package-on-Package (PoP) Multi Level Package (fcPoP-MLP) structure is further developed as shown in Fig.2. The solder balls in direct contact with the top surface of the bottom package and those in direct contact with the bottom surface of the top package provide electrically conductive pathways and mechanical supports to the assemblies. As shown in Fig. 2, a die is located on a laminate substrate in a flip chip style and encapsulated in the bottom package. The bottom package can be further mounted to PCB in a BGA method through the solder balls below the laminate substrate. A substrate interposer is included as a structural component on the bottom package. A top package or multi packages can be stacked on the substrate interposer, and thus electrically and thermally connected through the substrate interposer, the stacked solder balls, the laminate substrate and finally to the PCB in Fig. 2. Furthermore, in order to solve the weak structural problem, copper pillars are formed in Fig. 3 to replace the soft solder balls in direct with the substrate.

Fig. 2 Flip Chip PoP Multi Level Package (fcPoP-MLP) structure with an interposer and solder balls


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Method for eWLB and Flipchip PoP with Routed Leadframe Interposer

Fig. 3 Flip Chip PoP Multi Level Package (fcPoP-MLP) structure with solder balls and copper pillars

The structure of a Quad Flat Non-lead (QFN) package with multirow lead frame stands is already disclosed in the prior art. The cross-sectional view, the top view and the bottom view are shown in Fig. 4. Die pad section are located at the center of the lead frame; while the un- etched studs are formed at the periphery. Pre-plated frames (PPF) of NiPd or silver platings are formed both on the top and...