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PoP with Dielectric-less Interposer

IP.com Disclosure Number: IPCOM000247981D
Publication Date: 2016-Oct-14
Document File: 6 page(s) / 355K

Publishing Venue

The IP.com Prior Art Database

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PoP with Dielectric-less Interposer

Background

Various Package-on-package (PoP) structures have been developed for many applications, such as hand phones and other portable devices in which the circuit board space is limited. The PoP technology faces a major challenge of reducing the interconnect pitch between the top package and the bottom package. The bus width between the top and the bottom packages increases continuously, but the interconnect pitch between the top and the bottom substrates can only accommodate a certain number of signals. The molded-embedded PoP (MeP) technology has been raised to solve the small-pitch requirement. In the MeP structure shown in Fig. 1, an additional laminate interposer may be included on the bottom package. The additional interposer can redistribute signals to accommodate signals to and from the dies in the top package. In Fig. 1, copper core solder balls (CCSB) are embedded after molding and adopted as interconnects with the bottom portion connected to the laminate substrate and the top portion connected to the laminate interposer.

Fig. 1 A Molded-embedded PoP (MeP) structure with a laminate interposer on the bottom package

The technology of Flip Chip Package-on-Package (PoP) Multi Level Package (fcPoP-MLP) structure is further developed as shown in Fig.2. A copper post interposer is mounted onto the laminate substrate with a flip chip die. Copper posts on the bottom surface of the interposer are in direct contact with the solder balls on the top surface of the laminate substrate, both of which provide electrically conductive pathways and mechanical supports to the top package. As shown in Fig. 2, a die is located on a laminate substrate in a flip chip style and encapsulated in the bottom package. The bottom package can be further mounted to PCB in a BGA method through the solder balls below the laminate substrate. A substrate interposer is included as a structural component on the bottom package. A top package or multi packages can be stacked on the substrate interposer, and thus electrically and thermally connected through the substrate interposer, the copper posts, the solder balls, the laminate substrate and finally to the PCB.


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PoP with Dielectric-less Interposer

Fig. 2 Flip Chip PoP Multi Level Package (fcPoP-MLP) structure with a copper post interposer

Embedded Wafer Level Ball Grid Array (eWLB) is a packaging technology for integrated circuits, which is a further development of Wafer Level Ball Grid Array (WLB) technology. A double sided eWLB-PoP structure is shown in Fig. 3, with a redistribution layer (RDL) at the bottom package and another RDL on the top package. No interposer is used to connect the top package and the bottom package.

Fig. 3 A double sided eWLB PoP structure

A eWLB-PoP structure with PCB bars is shown in Fig. 4. PCB bars are placed at the periphery of the bottom package, instead of solder balls and copper posts in Fig. 2. A laminate interposer is insta...