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Stepped Ball Pad Embedded Trace Substrate

IP.com Disclosure Number: IPCOM000247989D
Publication Date: 2016-Oct-14
Document File: 7 page(s) / 231K

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Stepped Ball Pad Embedded Trace Substrate

Background

Semiconductor devices are widely used in modern electronic products. One goal of semiconductor manufacturing is to produce smaller, thinner and weight-lighter devices used in various products such as mobile phone, PDA and digital camera. Therefore, the chips insides such devices require a smaller overall volume, a bigr number of I/O ports and better electrical properties. As the number of I/O ports increases, the pitch of the integrated circuit is reduced.

In recent years, chip carriers with embedded passive components or traces have been raised up as functional substrates to meet the technical need above. Thus the Embedded Trace Substrate (ETS) possessing electrical properties are taught in several patent disclosures. In US patent publication 20130026657, a method is proposed to produce a wiring substrate, in which a semiconductor chip is electrically connected to the internal connection pads and external connection terminals are provided on the external connection pads. US patent 8017436 discloses a method of fabricating thin substrate, including forming a circuit pattern on a first carrier and embedding the circuit pattern in a dielectric material on a second carrier. Laser-ablated artifacts are formed in the buildup dielectric material and filled with an electrically conductive material to form a buildup circuit pattern. In US patent publication 20100289132, a functional substrate is fabricated including a first patterned dielectric layer, a single patterned metal layer, and a second patterned dielectric layer. The single patterned metal layer is embedded in the first patterned dielectric layer. In US patent publication 20110084370, a carrier is fabricated, including a dielectric layer with openings, a patterned conductive layer, electrically conductive posts, and a patterned solder resist layer. The patterned conductive layer is embedded in the dielectric layer and is disposed adjacent to the first surface of the dielectric layer. In US patent publication 20110186342, a single layered printed circuit board is taught with a higher density. The fabricating method includes forming a bonding pad, a circuit pattern and a post on a surface of an insulation film; pressing an insulator on the surface of the insulation film, in which the circuit pattern and the post are buried in the insulator; selectively etching the insulator so that the other end part of the post is exposed; and opening a portion of the insulation film so that at least a portion of the bonding pad is exposed. In US patent publication 20130026657, a semiconductor assembly is proposed with a flexible layout, in which it is not necessary for the ball-implanting pads to be associated with the conductive pads in position. The assembly has an adjustable ball- implanting area, and thus the number of conductive traces can be adjusted for flexible trace routing.

Description

This invention discloses a single and multiple...