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Novel Process to Form Wavy Channel for Long Channel VFET

IP.com Disclosure Number: IPCOM000248027D
Publication Date: 2016-Oct-19
Document File: 5 page(s) / 179K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method and structure to use a wavy type channel to form long and short channel vertical Field Effect Transistors (VFETs) together.

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Novel Process to Form Wavy Channel for Long Channel VFET

A vertical Field Effect Transistors (VFET) can be a promising candidate for 5nm and beyond nodes; however, making long channel VFETs together with the short channel is a challenge.

A method is needed to produce long and short channel VFETs together.

The novel contribution is a method and structure to use a wavy type channel to form long and short channel VFETs together.

The following figures illustrate the components and process for implementing the wavy type channel solution.

Figure 1: Start with Silicon Germanium (SiGe) on Insulators

Figure 2: Shallow Trench Isolation (STI) formation and SiGe Fin Hard Mask (HM) open

Figure 3: Etch SiGe fin

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Figure 4: Strip HM

Figure 5: Epi grows Si channel on top of SiGe fin through cladding

Figure 6: Form sacrificial spacer and then dope n+ and p+ separately (here use n+ as an example)

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Figure 7: Strip spacer and then selective remove SiGe

Figure 8: Deposit sacrificial layer such as flow able oxide and then recess to the target thick

Figure 9: Deposit low K spacer. A heavy n and p dop can be done after the spacer for further resistance reduction.

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Figure 10: Deposit the Silicon Nitride (SiN) liner

Figure 11: Selective remove sacrificial layer

Figure 12: High K metal gate stack formation

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Figure 13: Deposit Inter-Layer Dialectric (ILD) and Chemical-Mechanical Planarization (CMP) to target thickness. Open the top Sou...