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Embedded Wafer Level Flip Chip Packaging

IP.com Disclosure Number: IPCOM000248047D
Publication Date: 2016-Oct-21
Document File: 4 page(s) / 499K

Publishing Venue

The IP.com Prior Art Database

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Page 01 of 4

Embedded Wafer Level Flip Chip Packaging

Background

The standard embedded wafer level BGA (eWLB) package involves reconstitution, redistribution (RDL) and backend process phases. The reconstitution is associated with the initial forming of artificial wafer that is made of orderly aligned silicon chips in juztaposition with flat mold cast. The chip placement accuracy on the tape prior to molding is especially crucial to ensure subsequent precision required on the formations of dielectric layer, metalization layer, and I/O configuration in the RDL, whereby photolithography is taking
place during the course of process. Figure 1 is representing the singulated unit manner of the developed eWLB package out of the wafer form, after the dicing process in backend process.

Figure 1: Standard eWLB package

The embedded wafer level flip chip packaging of this invention helps to eliminate the high accuracy of die placement required during the reconstitution. By incorporating the concept of flipchip packaging, wherein the routing trace and bond pad connectivity structures are pre- composed by plating on the etchable carrier for chip placement, this can mitigate the formidable risk of chip placement issue. Having said that, the flip chip solder bumps are connected with the configured bond pads on the carrier, literally get rid of the foremost dielectric coating on artificial wafer for the standard eWLB. Thus, embedded wafer level flip chip is able to reduce one layer of dielectric in the existing single and multiple metal layers WLB package. Moreover, it is a viable low cost solution for first Cu layer metalization by means of plating, which is a cheaper and simpler approach compared to employing the lithography process in RDL. The embedded wafer level flipchip package is shown in Figure 2A for single metal layer, while 2B for dual metal layers. The illustrations are not only limited to a flip chip, but it can be a diversity of multiple chips and passive components in the package.

Figure 2A:Single metal layer embedded wafer level flipchip package


Page 02 of 4

Embedded Wafer Level Flip Chip Packaging

Figure 2B:Dual metal layers embedded wafer level flipchip package

Description

The single metal layer embedded wafer level flip chip procedure is initialized with the preparation of an etchable metal strip or carrier, such as Cu or SPCC in standard rectangular panel or circular wafer. It is arbitrarily variable in shape and size by process capability. A conductive metal layer or a combination formation of multiple conductive metal layers, such as Cu/Ni-Au/PPF is selectively plated on top of carrier for the first circuitry metal trace layer including bond pads as shown in Figure 3A. The flip chip with solder bumps is then attached to the patterned bond pads, it may proceed to use epoxy or underfill material to fill the gap underneath the flip chip, followed by molding process in respective Figures 3B & 3C. Alternatively, right after the flipchip with so...