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Low Cost MIS Cavity Substrate Disclosure Number: IPCOM000248058D
Publication Date: 2016-Oct-21
Document File: 6 page(s) / 487K

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Page 01 of 6

Low Cost MIS Cavity Substrate


Cavity interposer is contributing to improve the physical package density and size for PoP application. This interposer is generally known to form as laminate based structure, which remains to be expensive since involved substrate process technology. Current laminate based interposer substrate also has limitation in routing at the cavity layer, unless additional dielectric layer is used which would incur additional cost.

This invention leverages on low baseline cost and simpler technology of Molded Interconnect Substrate (MIS) to produce MIS substrate with cavity. It teaches a method of creating the cavity without employing complicated procedures that used for conventional laminate cavity substrate, which is illustrated in the next section.


The MIS cavity interposer of single metal layer as shown in Figure 2K is conceptualized as it is in Figure 1A, for an exemplary interposer integrated in flip chip PoP application. It is contributing to higher I/O density to be a substrate structure of the top package in POP application. For an instance in Figure 1B, it is used as wire bond substrate on top of flip chip package. The diversity on integration of MIS cavity interposer is somehow variable depends on the user-defined requirements.

Figure 1A: Single metal layer MIS Cavity Interposer as it is an interposer

Figure 1B: MIS Cavity Interposer as a substrate for top package

Page 02 of 6

Low Cost MIS Cavity Substrate

The fabrication of single metal layer MIS cavity interposer is started with a panel of MIS carrier made of etchable material such as Cu or SPCC metal presented in Figure 2A. The carrier is deformed as in Figure 2B to create the structural cavity contour by stamping process generally available in basic leadframe forming technology. The patterning of ball and bump pad openings for interconnections between package to package is performed through initial photoresist or dry film lamination process as shown in Figure 2C, whereby a thin layer of patterned film is formed on top surface of the carrier, while having the openings for those pads at the outer cavity boundary. The openings are deposited with the conductive elements resistive to etching such as Au, AuNi or PPF as depicted in Figure 2D. This is followed by topping another photoresist layer or dry film, in which the narrower openings are corresponding in parallel with the initial pad size respectively. This means that the peripheral portions of the pads are overlapped by the relatively smaller openings of the second layer photoresist or dry film, namely the via holes as observed in Figure 2E. The via holes are filled with Cu through plating to form Cu via as shown in Figure 2F. Then, the two layers of the photoresist or dry film are removed by stripping process as in Figure 2G, and the mold process is proceeded by using mold compound or encapsulant to encapsulate the built-up structures on top of the carrier. Process of plana...