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Providing a Cavity to MIS Substrate By Cu Plating and Etching

IP.com Disclosure Number: IPCOM000248059D
Publication Date: 2016-Oct-21
Document File: 5 page(s) / 334K

Publishing Venue

The IP.com Prior Art Database

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Providing A Cavity to MIS Substrate by Cu Plating and Etching

Description

The MIS cavity interposer is conceptualized as it is in Figure 1A, for an exemplary interposer integrated in flip chip PoP application. It is contributing to higher I/O density to be a substrate structure of the top package in POP application. For an instance in Figure 1B, it is used as wire bond substrate on top of flip chip package. The diversity on application of MIS cavity interposer is somehow variable, which depends on the user-defined requirements.

Figure 1A: MIS Cavity Interposer as it is an interposer

Figure 1B: MIS Cavity Interposer as a substrate for top package

The fabrication of MIS cavity interposer is started with a panel of MIS carrier made of etchable material such as Cu or SPCC metal presented in Figure 2A. The primary photoresist or dry-film layer is applied on top surface of the carrier to pattern pad openings and create circumference center opening as shown in Figure 2B. The openings are deposited with the Cu element, which has equivalent thickness as photoresist or dry film. The Cu layer on the openings out of the circumference center area are formed as bottom ball pads or bump pads, while Cu layer at the center area as the cavity base in Figure 2C. This is followed by topping another photoresist or dry film layer depicted in Figure 2D, whereby it is thicker with narrower openings corresponding to the former openings of primary layer. This indicates the periphery of the first Cu plating layer are overlapped by the relatively smaller openings of the second layer photoresist or dry film, thus, via holes are formed corresponding to Cu pads and a recess is observed at the center by so-called cavity-form. Next, via holes are filled with Cu through plating to form Cu via pillars. Likewise, the Cu plating is performed on the center area initially plated with first Cu layer. The given Cu cavity-form, which is referring to the entire Cu layer at the center should appear relatively shallower compared to the surrounded Cu via pillars as shown in Figure 2E. Then, the photoresist or dry film layers are removed by stripping process as in Figure 2F. The mold process observed in Figure 2G is proceeded to over-mold the built-up structures on top of the carrier by using mold compound or


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Providing A Cavity to MIS Substrate by Cu Plating and Etching

encapsulant. Process of planarizing mold surface such as grinding and surface treatment as in Figure 2H is required to expose the tip of Cu via pillars for the next process. For the Cu via connectivity to form the top layer Cu traces and pads as shown in Figure 2I, the photo lithography patterning or plating is conducted using metal elements such as Cu, Au, AuNi or PPF. The solder resist layer is then applied on Cu trace to prevent oxidation as depicted in Figure 2J. The process is proceeded to remove the carrier through etching for subsequent bottom strip processing, thus, the bottom Cu pads and...