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Achieving Constant Delay in 1588 Aware Switching Devices

IP.com Disclosure Number: IPCOM000248138D
Publication Date: 2016-Oct-31
Document File: 2 page(s) / 196K

Publishing Venue

The IP.com Prior Art Database

Related People

Morten Terstrup: AUTHOR

Abstract

Achieving constant delay/fixed latency in network elements is an important feature of timing sensitive networks. This disclosure describes how system timers can be utilized to guarantee fixed latency in 1588 devices. By including the ingress timestamp in frames to the very boundary of the egress MAC, and knowing the maximum delay for uncongested traffic through the switching core, frame transmission can be suspended until the maximum delay is reached. The graph below illustrates the effect. Orange curve shows the delay variations without enabling the "Fixed Latency" functionality. Green curve shows the packet latency with "Fixed Latency" enabled.

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Achieving Constant Delay in 1588 Aware Switching Devices

       

BACKGROUND/SUMMARY

Achieving constant delay/fixed latency in network elements is an important feature of timing sensitive networks. This disclosure describes how system timers can be utilized to guarantee fixed latency in 1588 devices.

By including the ingress timestamp in frames to the very boundary of the egress MAC, and knowing the maximum delay for uncongested traffic through the switching core, frame transmission can be suspended until the maximum delay is reached. The graph below illustrates the effect. Orange curve shows the delay variations without enabling the “Fixed Latency” functionality. Green curve shows the packet latency with “Fixed Latency” enabled.

Figure 1: Forwarding delay diagram

DETAILED DESCRIPTION

A 1588 timing aware processing device will have the basic architecture as shown on Figure 2. A timing control module will provide time-of-day information to be used for determining when data arrived, and when data left the device. The timing information may be used for software processing, or for in-flight data manipulation.

Figure 2: Data transfer architecture

The data path through such a system might store incoming data in a storage for delayed transmission, store-and-forward transfer – or it might pass directly towards the egress, cut-through transfer.

In case of cut-through transfers, it can be desired to have a fixed delay through the device. That cannot be accomplished –...