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Low Cost Substrate Manufacturing Method and the Structure with Cu Post

IP.com Disclosure Number: IPCOM000248203D
Publication Date: 2016-Nov-09
Document File: 7 page(s) / 404K

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The IP.com Prior Art Database

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Low Cost Substrate Manufacturing Method and the Structure with Cu Post

Background

Semiconductor devices are widely used in modern electronic products. But high cost is a particular concern when the costly substrates are used in the price sensitive products, such as consumer products telecom markets. Therefore, low cost substrates and the manufacture methods are investigated. For example, US 2009/0321873 A1 discloses a low cost substrate having high-resistivity properties and methods for their manufacture, which provides reduced signal loss.

The copper posts on the substrate enable a higher stand-off height between the chip and the substrate and better capability to carry higher current when the current flows from the substrate to the chip. Therefore, copper posts are also widely used to enhance the robustness for fine pitch or large die wafer-level chip scale packaging (WLCSP). The copper post WLCSP process requires three lithographic masks, including a first polymer insulating layer, a redistribution line and an under bump metallurgy/copper post. Alternatively, the copper post WLCSP process requires four lithographic masks, with an additional second polymer insulating layer. But photo lithographic operations are a significant portion of semiconductor manufacture cost, not to mention the costs of photo masks.

Therefore, there is an urgent need for a low cost substrate with copper posts, which the subject invention is intended for.

Description

This invention discloses a low cost substrate with copper posts and the manufacturing method thereof. The subject invention has several major advantages over the conventional substrate with copper posts, which will be described in detail later.

The two-layer conventional substrate with copper posts is shown in Fig. 1. Copper pads and solder resist layers are formed on the top and bottom surfaces of the carrier. On the bottom side of the carrier, copper posts are formed on the copper pads at the periphery of the structure, and further protrude out of the solder resist layer. As shown in Fig. 1, the copper posts are connected to the copper pads on the bottom side, to the through copper vias in the insulator, and further to the copper pads on the top side of the structure.

Fig. 1 The two-layer conventional substrate with copper posts


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Low Cost Substrate Manufacturing Method and the Structure with Cu Post

The copper post formation processes of the two-layer conventional substrate with copper posts are shown in Fig. 2. First, on the top side of the structure, a seed layer is formed on the top surface of the solder resist layer at the periphery and the exposed copper pad in the middle, after the processes of solder resist formation and surface finish. The solder resist layer is thicker than that of the copper pad and thus a recess is formed on the top of the exposed copper pad in the middle of the structure. Second, a dry film is partially formed on the top surface of the solder resist...