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Cavity Molded Interconnect Substrate (CMIS)

IP.com Disclosure Number: IPCOM000248219D
Publication Date: 2016-Nov-10
Document File: 3 page(s) / 372K

Publishing Venue

The IP.com Prior Art Database

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Cavity Molded Interconnect Substrate (CMIS)

Background

A common semiconductor device arrangement includes an upper semiconductor package stacked over a lower semiconductor package, i.e. package-on-package (PoP). The upper semiconductor package is typically electrically connected with a substrate. A need exists for a substrate for PoP with reduced package height and lower manufacturing cost.

Disclosed is a substrate as part of the interconnect structure inserted into semiconductor packages such as PoP and manufacturing method thereof. Insulation of the substrate is formed of epoxy molding compounds (EMC) instead of prepreg (PPG) which is typically used to form insulation. In addition, a substrate has a cavity, which position can be followed as the semiconductor chip on the bottom package. Since the cavity accommodates the semiconductor chip, whole package height is able to be reduced.

Description

As shown in Fig. 1, a carrier is provided. The carrier is preferably copper core laminate (CCL).

Fig. 2 shows forming a first trace layer. The photo-resist layer is disposed on the top surface of a carrier. For example, the photo-resist layer is a positive type. A photo mask with pattern design is disposed above the photo-resist layer such that the photo-resist layer is selectively exposed to the radiation. The exposed portion is removed in the developing process. A first trace layer is formed on the patterned openings. The first trace layer can be formed by plating, and preferably has more than one layer, whose material is Cu, Ni, Au, or Sn. Afterwards, the patterned photo-resist layer is removed, and the first trace layer is retained on the carrier.

Fig. 3 shows forming vertical connection on the first trace layer. The photo-resist layer is formed on the carrier and covers the first trace layer. For example, the photo-resist layer is a positive type. A photo mask with pattern design is disposed above the photo-resist layer such that the photo-resist layer is selectively exposed to the radiation. The exposed portion is removed in the developing process. Vertical connection is formed on the patterned openings.


Page 02 of 3

Cavity Molded Interconnect Substrate (CMIS)

Vertical connection can be formed by plating, and the material is preferably Cu or solder. Afterwards, the patterned photo-resist layer is removed, and the vertical connection is retained on the first trace layer and the carrier.

Fig. 4 ~ Fig. 6 shows forming insulation layer having a cavity. A mold chase having a protrusion is used for forming a cavity on the molding material layer. A molding material layer is formed for covering the first conductiv...